Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
   8
   9 maintainers:
  10   - Daire McNamara <daire.mcnamara@microchip.com>
  11
  12 allOf:
  13   - $ref: /schemas/pci/pci-bus.yaml#
  14
  15 properties:
  16   compatible:
  17     const: microchip,pcie-host-1.0 # PolarFire
  18
  19   reg:
  20     maxItems: 2
  21
  22   reg-names:
  23     items:
  24       - const: cfg
  25       - const: apb
  26
  27   interrupts:
  28     minItems: 1
  29     maxItems: 2
  30     items:
  31       - description: PCIe host controller
  32       - description: builtin MSI controller
  33
  34   interrupt-names:
  35     minItems: 1
  36     maxItems: 2
  37     items:
  38       - const: pcie
  39       - const: msi
  40
  41   ranges:
  42     maxItems: 1
  43
  44   msi-controller:
  45     description: Identifies the node as an MSI controller.
  46
  47   msi-parent:
  48     description: MSI controller the device is capable of using.
  49
  50 required:
  51   - reg
  52   - reg-names
  53   - "#interrupt-cells"
  54   - interrupts
  55   - interrupt-map-mask
  56   - interrupt-map
  57   - msi-controller
  58
  59 unevaluatedProperties: false
  60
  61 examples:
  62   - |
  63     soc {
  64             #address-cells = <2>;
  65             #size-cells = <2>;
  66             pcie0: pcie@2030000000 {
  67                     compatible = "microchip,pcie-host-1.0";
  68                     reg = <0x0 0x70000000 0x0 0x08000000>,
  69                           <0x0 0x43000000 0x0 0x00010000>;
  70                     reg-names = "cfg", "apb";
  71                     device_type = "pci";
  72                     #address-cells = <3>;
  73                     #size-cells = <2>;
  74                     #interrupt-cells = <1>;
  75                     interrupts = <119>;
  76                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  77                     interrupt-map = <0 0 0 1 &pcie_intc0 0>,
  78                                     <0 0 0 2 &pcie_intc0 1>,
  79                                     <0 0 0 3 &pcie_intc0 2>,
  80                                     <0 0 0 4 &pcie_intc0 3>;
  81                     interrupt-parent = <&plic0>;
  82                     msi-parent = <&pcie0>;
  83                     msi-controller;
  84                     bus-range = <0x00 0x7f>;
  85                     ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
  86                     pcie_intc0: interrupt-controller {
  87                         #address-cells = <0>;
  88                         #interrupt-cells = <1>;
  89                         interrupt-controller;
  90                     };
  91             };
  92     };