Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Gen3 PCIe controller on MediaTek SoCs
   8
   9 maintainers:
  10   - Jianjun Wang <jianjun.wang@mediatek.com>
  11
  12 description: |+
  13   PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
  14   and compatible with Gen2, Gen1 speed.
  15
  16   This PCIe controller supports up to 256 MSI vectors, the MSI hardware
  17   block diagram is as follows:
  18
  19                     +-----+
  20                     | GIC |
  21                     +-----+
  22                        ^
  23                        |
  24                    port->irq
  25                        |
  26                +-+-+-+-+-+-+-+-+
  27                |0|1|2|3|4|5|6|7| (PCIe intc)
  28                +-+-+-+-+-+-+-+-+
  29                 ^ ^           ^
  30                 | |    ...    |
  31         +-------+ +------+    +-----------+
  32         |                |                |
  33   +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
  34   |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
  35   +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
  36    ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
  37    | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
  38    | |      |  |    | |      |  |    | |      |  |
  39
  40     (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
  41
  42   With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
  43   each set has its own address for MSI message, and supports 32 MSI vectors
  44   to generate interrupt.
  45
  46 properties:
  47   compatible:
  48     oneOf:
  49       - items:
  50           - enum:
  51               - mediatek,mt7986-pcie
  52               - mediatek,mt8188-pcie
  53               - mediatek,mt8195-pcie
  54           - const: mediatek,mt8192-pcie
  55       - const: mediatek,mt8192-pcie
  56
  57   reg:
  58     maxItems: 1
  59
  60   reg-names:
  61     items:
  62       - const: pcie-mac
  63
  64   interrupts:
  65     maxItems: 1
  66
  67   ranges:
  68     minItems: 1
  69     maxItems: 8
  70
  71   iommu-map:
  72     maxItems: 1
  73
  74   iommu-map-mask:
  75     const: 0
  76
  77   resets:
  78     minItems: 1
  79     maxItems: 2
  80
  81   reset-names:
  82     minItems: 1
  83     maxItems: 2
  84     items:
  85       enum: [ phy, mac ]
  86
  87   clocks:
  88     minItems: 4
  89     maxItems: 6
  90
  91   clock-names:
  92     minItems: 4
  93     maxItems: 6
  94
  95   assigned-clocks:
  96     maxItems: 1
  97
  98   assigned-clock-parents:
  99     maxItems: 1
 100
 101   phys:
 102     maxItems: 1
 103
 104   phy-names:
 105     items:
 106       - const: pcie-phy
 107
 108   power-domains:
 109     maxItems: 1
 110
 111   '#interrupt-cells':
 112     const: 1
 113
 114   interrupt-controller:
 115     description: Interrupt controller node for handling legacy PCI interrupts.
 116     type: object
 117     properties:
 118       '#address-cells':
 119         const: 0
 120       '#interrupt-cells':
 121         const: 1
 122       interrupt-controller: true
 123
 124     required:
 125       - '#address-cells'
 126       - '#interrupt-cells'
 127       - interrupt-controller
 128
 129     additionalProperties: false
 130
 131 required:
 132   - compatible
 133   - reg
 134   - reg-names
 135   - interrupts
 136   - ranges
 137   - clocks
 138   - clock-names
 139   - '#interrupt-cells'
 140   - interrupt-controller
 141
 142 allOf:
 143   - $ref: /schemas/pci/pci-bus.yaml#
 144   - if:
 145       properties:
 146         compatible:
 147           const: mediatek,mt8192-pcie
 148     then:
 149       properties:
 150         clock-names:
 151           items:
 152             - const: pl_250m
 153             - const: tl_26m
 154             - const: tl_96m
 155             - const: tl_32k
 156             - const: peri_26m
 157             - const: top_133m
 158   - if:
 159       properties:
 160         compatible:
 161           contains:
 162             enum:
 163               - mediatek,mt8188-pcie
 164               - mediatek,mt8195-pcie
 165     then:
 166       properties:
 167         clock-names:
 168           items:
 169             - const: pl_250m
 170             - const: tl_26m
 171             - const: tl_96m
 172             - const: tl_32k
 173             - const: peri_26m
 174             - const: peri_mem
 175   - if:
 176       properties:
 177         compatible:
 178           contains:
 179             enum:
 180               - mediatek,mt7986-pcie
 181     then:
 182       properties:
 183         clock-names:
 184           items:
 185             - const: pl_250m
 186             - const: tl_26m
 187             - const: peri_26m
 188             - const: top_133m
 189
 190 unevaluatedProperties: false
 191
 192 examples:
 193   - |
 194     #include <dt-bindings/interrupt-controller/arm-gic.h>
 195     #include <dt-bindings/interrupt-controller/irq.h>
 196
 197     bus {
 198         #address-cells = <2>;
 199         #size-cells = <2>;
 200
 201         pcie: pcie@11230000 {
 202             compatible = "mediatek,mt8192-pcie";
 203             device_type = "pci";
 204             #address-cells = <3>;
 205             #size-cells = <2>;
 206             reg = <0x00 0x11230000 0x00 0x4000>;
 207             reg-names = "pcie-mac";
 208             interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
 209             bus-range = <0x00 0xff>;
 210             ranges = <0x82000000 0x00 0x12000000 0x00
 211                       0x12000000 0x00 0x1000000>;
 212             clocks = <&infracfg 44>,
 213                      <&infracfg 40>,
 214                      <&infracfg 43>,
 215                      <&infracfg 97>,
 216                      <&infracfg 99>,
 217                      <&infracfg 111>;
 218             clock-names = "pl_250m", "tl_26m", "tl_96m",
 219                           "tl_32k", "peri_26m", "top_133m";
 220             assigned-clocks = <&topckgen 50>;
 221             assigned-clock-parents = <&topckgen 91>;
 222
 223             phys = <&pciephy>;
 224             phy-names = "pcie-phy";
 225
 226             resets = <&infracfg_rst 2>,
 227                      <&infracfg_rst 3>;
 228             reset-names = "phy", "mac";
 229
 230             #interrupt-cells = <1>;
 231             interrupt-map-mask = <0 0 0 0x7>;
 232             interrupt-map = <0 0 0 1 &pcie_intc 0>,
 233                             <0 0 0 2 &pcie_intc 1>,
 234                             <0 0 0 3 &pcie_intc 2>,
 235                             <0 0 0 4 &pcie_intc 3>;
 236             pcie_intc: interrupt-controller {
 237                       #address-cells = <0>;
 238                       #interrupt-cells = <1>;
 239                       interrupt-controller;
 240             };
 241         };
 242     };