Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Gen3 PCIe controller on MediaTek SoCs
   8
   9 maintainers:
  10   - Jianjun Wang <jianjun.wang@mediatek.com>
  11
  12 description: |+
  13   PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
  14   and compatible with Gen2, Gen1 speed.
  15
  16   This PCIe controller supports up to 256 MSI vectors, the MSI hardware
  17   block diagram is as follows:
  18
  19                     +-----+
  20                     | GIC |
  21                     +-----+
  22                        ^
  23                        |
  24                    port->irq
  25                        |
  26                +-+-+-+-+-+-+-+-+
  27                |0|1|2|3|4|5|6|7| (PCIe intc)
  28                +-+-+-+-+-+-+-+-+
  29                 ^ ^           ^
  30                 | |    ...    |
  31         +-------+ +------+    +-----------+
  32         |                |                |
  33   +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
  34   |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
  35   +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
  36    ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
  37    | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
  38    | |      |  |    | |      |  |    | |      |  |
  39
  40     (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
  41
  42   With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
  43   each set has its own address for MSI message, and supports 32 MSI vectors
  44   to generate interrupt.
  45
  46 allOf:
  47   - $ref: /schemas/pci/pci-bus.yaml#
  48
  49 properties:
  50   compatible:
  51     const: mediatek,mt8192-pcie
  52
  53   reg:
  54     maxItems: 1
  55
  56   reg-names:
  57     items:
  58       - const: pcie-mac
  59
  60   interrupts:
  61     maxItems: 1
  62
  63   ranges:
  64     minItems: 1
  65     maxItems: 8
  66
  67   resets:
  68     minItems: 1
  69     maxItems: 2
  70
  71   reset-names:
  72     minItems: 1
  73     items:
  74       - const: phy
  75       - const: mac
  76
  77   clocks:
  78     maxItems: 6
  79
  80   clock-names:
  81     items:
  82       - const: pl_250m
  83       - const: tl_26m
  84       - const: tl_96m
  85       - const: tl_32k
  86       - const: peri_26m
  87       - const: top_133m
  88
  89   assigned-clocks:
  90     maxItems: 1
  91
  92   assigned-clock-parents:
  93     maxItems: 1
  94
  95   phys:
  96     maxItems: 1
  97
  98   phy-names:
  99     items:
 100       - const: pcie-phy
 101
 102   '#interrupt-cells':
 103     const: 1
 104
 105   interrupt-controller:
 106     description: Interrupt controller node for handling legacy PCI interrupts.
 107     type: object
 108     properties:
 109       '#address-cells':
 110         const: 0
 111       '#interrupt-cells':
 112         const: 1
 113       interrupt-controller: true
 114
 115     required:
 116       - '#address-cells'
 117       - '#interrupt-cells'
 118       - interrupt-controller
 119
 120     additionalProperties: false
 121
 122 required:
 123   - compatible
 124   - reg
 125   - reg-names
 126   - interrupts
 127   - ranges
 128   - clocks
 129   - '#interrupt-cells'
 130   - interrupt-controller
 131
 132 unevaluatedProperties: false
 133
 134 examples:
 135   - |
 136     #include <dt-bindings/interrupt-controller/arm-gic.h>
 137     #include <dt-bindings/interrupt-controller/irq.h>
 138
 139     bus {
 140         #address-cells = <2>;
 141         #size-cells = <2>;
 142
 143         pcie: pcie@11230000 {
 144             compatible = "mediatek,mt8192-pcie";
 145             device_type = "pci";
 146             #address-cells = <3>;
 147             #size-cells = <2>;
 148             reg = <0x00 0x11230000 0x00 0x4000>;
 149             reg-names = "pcie-mac";
 150             interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
 151             bus-range = <0x00 0xff>;
 152             ranges = <0x82000000 0x00 0x12000000 0x00
 153                       0x12000000 0x00 0x1000000>;
 154             clocks = <&infracfg 44>,
 155                      <&infracfg 40>,
 156                      <&infracfg 43>,
 157                      <&infracfg 97>,
 158                      <&infracfg 99>,
 159                      <&infracfg 111>;
 160             clock-names = "pl_250m", "tl_26m", "tl_96m",
 161                           "tl_32k", "peri_26m", "top_133m";
 162             assigned-clocks = <&topckgen 50>;
 163             assigned-clock-parents = <&topckgen 91>;
 164
 165             phys = <&pciephy>;
 166             phy-names = "pcie-phy";
 167
 168             resets = <&infracfg_rst 2>,
 169                      <&infracfg_rst 3>;
 170             reset-names = "phy", "mac";
 171
 172             #interrupt-cells = <1>;
 173             interrupt-map-mask = <0 0 0 0x7>;
 174             interrupt-map = <0 0 0 1 &pcie_intc 0>,
 175                             <0 0 0 2 &pcie_intc 1>,
 176                             <0 0 0 3 &pcie_intc 2>,
 177                             <0 0 0 4 &pcie_intc 3>;
 178             pcie_intc: interrupt-controller {
 179                       #address-cells = <0>;
 180                       #interrupt-cells = <1>;
 181                       interrupt-controller;
 182             };
 183         };
 184     };