Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Freescale i.MX6 PCIe Endpoint controller
   8
   9 maintainers:
  10   - Lucas Stach <l.stach@pengutronix.de>
  11   - Richard Zhu <hongxing.zhu@nxp.com>
  12
  13 description: |+
  14   This PCIe controller is based on the Synopsys DesignWare PCIe IP and
  15   thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
  16   The controller instances are dual mode where in they can work either in
  17   Root Port mode or Endpoint mode but one at a time.
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - fsl,imx8mm-pcie-ep
  23       - fsl,imx8mq-pcie-ep
  24       - fsl,imx8mp-pcie-ep
  25       - fsl,imx95-pcie-ep
  26
  27   clocks:
  28     minItems: 3
  29     items:
  30       - description: PCIe bridge clock.
  31       - description: PCIe bus clock.
  32       - description: PCIe PHY clock.
  33       - description: Additional required clock entry for imx6sx-pcie,
  34            imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
  35
  36   clock-names:
  37     minItems: 3
  38     maxItems: 4
  39
  40   interrupts:
  41     items:
  42       - description: builtin eDMA interrupter.
  43
  44   interrupt-names:
  45     items:
  46       - const: dma
  47
  48 required:
  49   - compatible
  50   - reg
  51   - reg-names
  52   - interrupts
  53   - interrupt-names
  54
  55 allOf:
  56   - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
  57   - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
  58   - if:
  59       properties:
  60         compatible:
  61           enum:
  62             - fsl,imx8mm-pcie-ep
  63             - fsl,imx8mq-pcie-ep
  64             - fsl,imx8mp-pcie-ep
  65     then:
  66       properties:
  67         reg:
  68           minItems: 2
  69           maxItems: 2
  70         reg-names:
  71           items:
  72             - const: dbi
  73             - const: addr_space
  74
  75   - if:
  76       properties:
  77         compatible:
  78           enum:
  79             - fsl,imx95-pcie-ep
  80     then:
  81       properties:
  82         reg:
  83           minItems: 6
  84           maxItems: 6
  85         reg-names:
  86           items:
  87             - const: dbi
  88             - const: atu
  89             - const: dbi2
  90             - const: app
  91             - const: dma
  92             - const: addr_space
  93
  94   - if:
  95       properties:
  96         compatible:
  97           enum:
  98             - fsl,imx8mq-pcie-ep
  99             - fsl,imx95-pcie-ep
 100     then:
 101       properties:
 102         clocks:
 103           minItems: 4
 104         clock-names:
 105           items:
 106             - const: pcie
 107             - const: pcie_bus
 108             - const: pcie_phy
 109             - const: pcie_aux
 110     else:
 111       properties:
 112         clocks:
 113           maxItems: 3
 114         clock-names:
 115           items:
 116             - const: pcie
 117             - const: pcie_bus
 118             - const: pcie_aux
 119
 120
 121 unevaluatedProperties: false
 122
 123 examples:
 124   - |
 125     #include <dt-bindings/clock/imx8mp-clock.h>
 126     #include <dt-bindings/power/imx8mp-power.h>
 127     #include <dt-bindings/reset/imx8mp-reset.h>
 128     #include <dt-bindings/interrupt-controller/arm-gic.h>
 129
 130     pcie_ep: pcie-ep@33800000 {
 131       compatible = "fsl,imx8mp-pcie-ep";
 132       reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
 133       reg-names = "dbi", "addr_space";
 134       clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
 135                <&clk IMX8MP_CLK_HSIO_AXI>,
 136                <&clk IMX8MP_CLK_PCIE_ROOT>;
 137       clock-names = "pcie", "pcie_bus", "pcie_aux";
 138       assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
 139       assigned-clock-rates = <10000000>;
 140       assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
 141       num-lanes = <1>;
 142       interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
 143       interrupt-names = "dma";
 144       fsl,max-link-speed = <3>;
 145       power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
 146       resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
 147                <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
 148       reset-names = "apps", "turnoff";
 149       phys = <&pcie_phy>;
 150       phy-names = "pcie-phy";
 151       num-ib-windows = <4>;
 152       num-ob-windows = <4>;
 153     };