1 Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
2 ===================================
4 For some SoCs, the CPU frequency subset and voltage value of each OPP
5 varies based on the silicon variant in use. Allwinner Process Voltage
6 Scaling Tables defines the voltage and frequency value based on the
7 speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
8 reads the efuse value from the SoC to provide the OPP framework with
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'allwinner,sun50i-h6-operating-points'.
19 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
20 efuse registers that has information about the speedbin
21 that is used to select the right frequency/voltage value
22 pair. Please refer the for nvmem-cells bindings
23 Documentation/devicetree/bindings/nvmem/nvmem.txt and
27 - opp-microvolt-<name>: Voltage in micro Volts.
28 At runtime, the platform can pick a <name> and
29 matching opp-microvolt-<name> property.
32 sun50i-h6 speed0 speed1 speed2
42 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 clocks = <&ccu CLK_CPUX>;
47 clock-latency-ns = <244144>; /* 8 32k periods */
48 operating-points-v2 = <&cpu_opp_table>;
53 compatible = "arm,cortex-a53";
56 enable-method = "psci";
57 clocks = <&ccu CLK_CPUX>;
58 clock-latency-ns = <244144>; /* 8 32k periods */
59 operating-points-v2 = <&cpu_opp_table>;
64 compatible = "arm,cortex-a53";
67 enable-method = "psci";
68 clocks = <&ccu CLK_CPUX>;
69 clock-latency-ns = <244144>; /* 8 32k periods */
70 operating-points-v2 = <&cpu_opp_table>;
75 compatible = "arm,cortex-a53";
78 enable-method = "psci";
79 clocks = <&ccu CLK_CPUX>;
80 clock-latency-ns = <244144>; /* 8 32k periods */
81 operating-points-v2 = <&cpu_opp_table>;
86 cpu_opp_table: opp_table {
87 compatible = "allwinner,sun50i-h6-operating-points";
88 nvmem-cells = <&speedbin_efuse>;
92 clock-latency-ns = <244144>; /* 8 32k periods */
93 opp-hz = /bits/ 64 <480000000>;
95 opp-microvolt-speed0 = <880000>;
96 opp-microvolt-speed1 = <820000>;
97 opp-microvolt-speed2 = <800000>;
101 clock-latency-ns = <244144>; /* 8 32k periods */
102 opp-hz = /bits/ 64 <720000000>;
104 opp-microvolt-speed0 = <880000>;
105 opp-microvolt-speed1 = <820000>;
106 opp-microvolt-speed2 = <800000>;
110 clock-latency-ns = <244144>; /* 8 32k periods */
111 opp-hz = /bits/ 64 <816000000>;
113 opp-microvolt-speed0 = <880000>;
114 opp-microvolt-speed1 = <820000>;
115 opp-microvolt-speed2 = <800000>;
119 clock-latency-ns = <244144>; /* 8 32k periods */
120 opp-hz = /bits/ 64 <888000000>;
122 opp-microvolt-speed0 = <940000>;
123 opp-microvolt-speed1 = <820000>;
124 opp-microvolt-speed2 = <800000>;
128 clock-latency-ns = <244144>; /* 8 32k periods */
129 opp-hz = /bits/ 64 <1080000000>;
131 opp-microvolt-speed0 = <1060000>;
132 opp-microvolt-speed1 = <880000>;
133 opp-microvolt-speed2 = <840000>;
137 clock-latency-ns = <244144>; /* 8 32k periods */
138 opp-hz = /bits/ 64 <1320000000>;
140 opp-microvolt-speed0 = <1160000>;
141 opp-microvolt-speed1 = <940000>;
142 opp-microvolt-speed2 = <900000>;
146 clock-latency-ns = <244144>; /* 8 32k periods */
147 opp-hz = /bits/ 64 <1488000000>;
149 opp-microvolt-speed0 = <1160000>;
150 opp-microvolt-speed1 = <1000000>;
151 opp-microvolt-speed2 = <960000>;
158 compatible = "allwinner,sun50i-h6-sid";
159 reg = <0x03006000 0x400>;
160 #address-cells = <1>;
163 speedbin_efuse: speed@1c {