Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt

   1 Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
   2 ===================================
   3
   4 For some SoCs, the CPU frequency subset and voltage value of each OPP
   5 varies based on the silicon variant in use. Allwinner Process Voltage
   6 Scaling Tables defines the voltage and frequency value based on the
   7 speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
   8 reads the efuse value from the SoC to provide the OPP framework with
   9 required information.
  10
  11 Required properties:
  12 --------------------
  13 In 'cpus' nodes:
  14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
  15
  16 In 'operating-points-v2' table:
  17 - compatible: Should be
  18         - 'allwinner,sun50i-h6-operating-points'.
  19 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
  20                 efuse registers that has information about the speedbin
  21                 that is used to select the right frequency/voltage value
  22                 pair. Please refer the for nvmem-cells bindings
  23                 Documentation/devicetree/bindings/nvmem/nvmem.txt and
  24                 also examples below.
  25
  26 In every OPP node:
  27 - opp-microvolt-<name>: Voltage in micro Volts.
  28                         At runtime, the platform can pick a <name> and
  29                         matching opp-microvolt-<name> property.
  30                         [See: opp.txt]
  31                         HW:             <name>:
  32                         sun50i-h6       speed0 speed1 speed2
  33
  34 Example 1:
  35 ---------
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         compatible = "arm,cortex-a53";
  43                         device_type = "cpu";
  44                         reg = <0>;
  45                         enable-method = "psci";
  46                         clocks = <&ccu CLK_CPUX>;
  47                         clock-latency-ns = <244144>; /* 8 32k periods */
  48                         operating-points-v2 = <&cpu_opp_table>;
  49                         #cooling-cells = <2>;
  50                 };
  51
  52                 cpu1: cpu@1 {
  53                         compatible = "arm,cortex-a53";
  54                         device_type = "cpu";
  55                         reg = <1>;
  56                         enable-method = "psci";
  57                         clocks = <&ccu CLK_CPUX>;
  58                         clock-latency-ns = <244144>; /* 8 32k periods */
  59                         operating-points-v2 = <&cpu_opp_table>;
  60                         #cooling-cells = <2>;
  61                 };
  62
  63                 cpu2: cpu@2 {
  64                         compatible = "arm,cortex-a53";
  65                         device_type = "cpu";
  66                         reg = <2>;
  67                         enable-method = "psci";
  68                         clocks = <&ccu CLK_CPUX>;
  69                         clock-latency-ns = <244144>; /* 8 32k periods */
  70                         operating-points-v2 = <&cpu_opp_table>;
  71                         #cooling-cells = <2>;
  72                 };
  73
  74                 cpu3: cpu@3 {
  75                         compatible = "arm,cortex-a53";
  76                         device_type = "cpu";
  77                         reg = <3>;
  78                         enable-method = "psci";
  79                         clocks = <&ccu CLK_CPUX>;
  80                         clock-latency-ns = <244144>; /* 8 32k periods */
  81                         operating-points-v2 = <&cpu_opp_table>;
  82                         #cooling-cells = <2>;
  83                 };
  84         };
  85
  86         cpu_opp_table: opp_table {
  87                 compatible = "allwinner,sun50i-h6-operating-points";
  88                 nvmem-cells = <&speedbin_efuse>;
  89                 opp-shared;
  90
  91                 opp@480000000 {
  92                         clock-latency-ns = <244144>; /* 8 32k periods */
  93                         opp-hz = /bits/ 64 <480000000>;
  94
  95                         opp-microvolt-speed0 = <880000>;
  96                         opp-microvolt-speed1 = <820000>;
  97                         opp-microvolt-speed2 = <800000>;
  98                 };
  99
 100                 opp@720000000 {
 101                         clock-latency-ns = <244144>; /* 8 32k periods */
 102                         opp-hz = /bits/ 64 <720000000>;
 103
 104                         opp-microvolt-speed0 = <880000>;
 105                         opp-microvolt-speed1 = <820000>;
 106                         opp-microvolt-speed2 = <800000>;
 107                 };
 108
 109                 opp@816000000 {
 110                         clock-latency-ns = <244144>; /* 8 32k periods */
 111                         opp-hz = /bits/ 64 <816000000>;
 112
 113                         opp-microvolt-speed0 = <880000>;
 114                         opp-microvolt-speed1 = <820000>;
 115                         opp-microvolt-speed2 = <800000>;
 116                 };
 117
 118                 opp@888000000 {
 119                         clock-latency-ns = <244144>; /* 8 32k periods */
 120                         opp-hz = /bits/ 64 <888000000>;
 121
 122                         opp-microvolt-speed0 = <940000>;
 123                         opp-microvolt-speed1 = <820000>;
 124                         opp-microvolt-speed2 = <800000>;
 125                 };
 126
 127                 opp@1080000000 {
 128                         clock-latency-ns = <244144>; /* 8 32k periods */
 129                         opp-hz = /bits/ 64 <1080000000>;
 130
 131                         opp-microvolt-speed0 = <1060000>;
 132                         opp-microvolt-speed1 = <880000>;
 133                         opp-microvolt-speed2 = <840000>;
 134                 };
 135
 136                 opp@1320000000 {
 137                         clock-latency-ns = <244144>; /* 8 32k periods */
 138                         opp-hz = /bits/ 64 <1320000000>;
 139
 140                         opp-microvolt-speed0 = <1160000>;
 141                         opp-microvolt-speed1 = <940000>;
 142                         opp-microvolt-speed2 = <900000>;
 143                 };
 144
 145                 opp@1488000000 {
 146                         clock-latency-ns = <244144>; /* 8 32k periods */
 147                         opp-hz = /bits/ 64 <1488000000>;
 148
 149                         opp-microvolt-speed0 = <1160000>;
 150                         opp-microvolt-speed1 = <1000000>;
 151                         opp-microvolt-speed2 = <960000>;
 152                 };
 153         };
 154 ....
 155 soc {
 156 ....
 157         sid: sid@3006000 {
 158                 compatible = "allwinner,sun50i-h6-sid";
 159                 reg = <0x03006000 0x400>;
 160                 #address-cells = <1>;
 161                 #size-cells = <1>;
 162                 ....
 163                 speedbin_efuse: speed@1c {
 164                         reg = <0x1c 4>;
 165                 };
 166         };
 167 };