Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt

   1 Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
   2 ===================================
   3
   4 In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
   5 the CPU frequencies subset and voltage value of each OPP varies based on
   6 the silicon variant in use.
   7 Qualcomm Technologies, Inc. Process Voltage Scaling Tables
   8 defines the voltage and frequency value based on the msm-id in SMEM
   9 and speedbin blown in the efuse combination.
  10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
  11 to provide the OPP framework with required information (existing HW bitmap).
  12 This is used to determine the voltage and frequency value for each OPP of
  13 operating-points-v2 table when it is parsed by the OPP framework.
  14
  15 Required properties:
  16 --------------------
  17 In 'cpu' nodes:
  18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
  19
  20 In 'operating-points-v2' table:
  21 - compatible: Should be
  22         - 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
  23                                              apq8064, ipq8064, msm8960 and ipq8074.
  24
  25 Optional properties:
  26 --------------------
  27 In 'cpu' nodes:
  28 - power-domains: A phandle pointing to the PM domain specifier which provides
  29                 the performance states available for active state management.
  30                 Please refer to the power-domains bindings
  31                 Documentation/devicetree/bindings/power/power_domain.txt
  32                 and also examples below.
  33 - power-domain-names: Should be
  34         - 'cpr' for qcs404.
  35
  36 In 'operating-points-v2' table:
  37 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
  38                 efuse registers that has information about the
  39                 speedbin that is used to select the right frequency/voltage
  40                 value pair.
  41                 Please refer the for nvmem-cells
  42                 bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
  43                 and also examples below.
  44
  45 In every OPP node:
  46 - opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
  47                     Bitmap:
  48                         0:      MSM8996 V3, speedbin 0
  49                         1:      MSM8996 V3, speedbin 1
  50                         2:      MSM8996 V3, speedbin 2
  51                         3:      unused
  52                         4:      MSM8996 SG, speedbin 0
  53                         5:      MSM8996 SG, speedbin 1
  54                         6:      MSM8996 SG, speedbin 2
  55                         7-31:   unused
  56
  57 Example 1:
  58 ---------
  59
  60         cpus {
  61                 #address-cells = <2>;
  62                 #size-cells = <0>;
  63
  64                 CPU0: cpu@0 {
  65                         device_type = "cpu";
  66                         compatible = "qcom,kryo";
  67                         reg = <0x0 0x0>;
  68                         enable-method = "psci";
  69                         clocks = <&kryocc 0>;
  70                         cpu-supply = <&pm8994_s11_saw>;
  71                         operating-points-v2 = <&cluster0_opp>;
  72                         #cooling-cells = <2>;
  73                         next-level-cache = <&L2_0>;
  74                         L2_0: l2-cache {
  75                               compatible = "cache";
  76                               cache-level = <2>;
  77                         };
  78                 };
  79
  80                 CPU1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "qcom,kryo";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                         clocks = <&kryocc 0>;
  86                         cpu-supply = <&pm8994_s11_saw>;
  87                         operating-points-v2 = <&cluster0_opp>;
  88                         #cooling-cells = <2>;
  89                         next-level-cache = <&L2_0>;
  90                 };
  91
  92                 CPU2: cpu@100 {
  93                         device_type = "cpu";
  94                         compatible = "qcom,kryo";
  95                         reg = <0x0 0x100>;
  96                         enable-method = "psci";
  97                         clocks = <&kryocc 1>;
  98                         cpu-supply = <&pm8994_s11_saw>;
  99                         operating-points-v2 = <&cluster1_opp>;
 100                         #cooling-cells = <2>;
 101                         next-level-cache = <&L2_1>;
 102                         L2_1: l2-cache {
 103                               compatible = "cache";
 104                               cache-level = <2>;
 105                         };
 106                 };
 107
 108                 CPU3: cpu@101 {
 109                         device_type = "cpu";
 110                         compatible = "qcom,kryo";
 111                         reg = <0x0 0x101>;
 112                         enable-method = "psci";
 113                         clocks = <&kryocc 1>;
 114                         cpu-supply = <&pm8994_s11_saw>;
 115                         operating-points-v2 = <&cluster1_opp>;
 116                         #cooling-cells = <2>;
 117                         next-level-cache = <&L2_1>;
 118                 };
 119
 120                 cpu-map {
 121                         cluster0 {
 122                                 core0 {
 123                                         cpu = <&CPU0>;
 124                                 };
 125
 126                                 core1 {
 127                                         cpu = <&CPU1>;
 128                                 };
 129                         };
 130
 131                         cluster1 {
 132                                 core0 {
 133                                         cpu = <&CPU2>;
 134                                 };
 135
 136                                 core1 {
 137                                         cpu = <&CPU3>;
 138                                 };
 139                         };
 140                 };
 141         };
 142
 143         cluster0_opp: opp_table0 {
 144                 compatible = "operating-points-v2-kryo-cpu";
 145                 nvmem-cells = <&speedbin_efuse>;
 146                 opp-shared;
 147
 148                 opp-307200000 {
 149                         opp-hz = /bits/ 64 <307200000>;
 150                         opp-microvolt = <905000 905000 1140000>;
 151                         opp-supported-hw = <0x77>;
 152                         clock-latency-ns = <200000>;
 153                 };
 154                 opp-384000000 {
 155                         opp-hz = /bits/ 64 <384000000>;
 156                         opp-microvolt = <905000 905000 1140000>;
 157                         opp-supported-hw = <0x70>;
 158                         clock-latency-ns = <200000>;
 159                 };
 160                 opp-422400000 {
 161                         opp-hz = /bits/ 64 <422400000>;
 162                         opp-microvolt = <905000 905000 1140000>;
 163                         opp-supported-hw = <0x7>;
 164                         clock-latency-ns = <200000>;
 165                 };
 166                 opp-460800000 {
 167                         opp-hz = /bits/ 64 <460800000>;
 168                         opp-microvolt = <905000 905000 1140000>;
 169                         opp-supported-hw = <0x70>;
 170                         clock-latency-ns = <200000>;
 171                 };
 172                 opp-480000000 {
 173                         opp-hz = /bits/ 64 <480000000>;
 174                         opp-microvolt = <905000 905000 1140000>;
 175                         opp-supported-hw = <0x7>;
 176                         clock-latency-ns = <200000>;
 177                 };
 178                 opp-537600000 {
 179                         opp-hz = /bits/ 64 <537600000>;
 180                         opp-microvolt = <905000 905000 1140000>;
 181                         opp-supported-hw = <0x70>;
 182                         clock-latency-ns = <200000>;
 183                 };
 184                 opp-556800000 {
 185                         opp-hz = /bits/ 64 <556800000>;
 186                         opp-microvolt = <905000 905000 1140000>;
 187                         opp-supported-hw = <0x7>;
 188                         clock-latency-ns = <200000>;
 189                 };
 190                 opp-614400000 {
 191                         opp-hz = /bits/ 64 <614400000>;
 192                         opp-microvolt = <905000 905000 1140000>;
 193                         opp-supported-hw = <0x70>;
 194                         clock-latency-ns = <200000>;
 195                 };
 196                 opp-652800000 {
 197                         opp-hz = /bits/ 64 <652800000>;
 198                         opp-microvolt = <905000 905000 1140000>;
 199                         opp-supported-hw = <0x7>;
 200                         clock-latency-ns = <200000>;
 201                 };
 202                 opp-691200000 {
 203                         opp-hz = /bits/ 64 <691200000>;
 204                         opp-microvolt = <905000 905000 1140000>;
 205                         opp-supported-hw = <0x70>;
 206                         clock-latency-ns = <200000>;
 207                 };
 208                 opp-729600000 {
 209                         opp-hz = /bits/ 64 <729600000>;
 210                         opp-microvolt = <905000 905000 1140000>;
 211                         opp-supported-hw = <0x7>;
 212                         clock-latency-ns = <200000>;
 213                 };
 214                 opp-768000000 {
 215                         opp-hz = /bits/ 64 <768000000>;
 216                         opp-microvolt = <905000 905000 1140000>;
 217                         opp-supported-hw = <0x70>;
 218                         clock-latency-ns = <200000>;
 219                 };
 220                 opp-844800000 {
 221                         opp-hz = /bits/ 64 <844800000>;
 222                         opp-microvolt = <905000 905000 1140000>;
 223                         opp-supported-hw = <0x77>;
 224                         clock-latency-ns = <200000>;
 225                 };
 226                 opp-902400000 {
 227                         opp-hz = /bits/ 64 <902400000>;
 228                         opp-microvolt = <905000 905000 1140000>;
 229                         opp-supported-hw = <0x70>;
 230                         clock-latency-ns = <200000>;
 231                 };
 232                 opp-960000000 {
 233                         opp-hz = /bits/ 64 <960000000>;
 234                         opp-microvolt = <905000 905000 1140000>;
 235                         opp-supported-hw = <0x7>;
 236                         clock-latency-ns = <200000>;
 237                 };
 238                 opp-979200000 {
 239                         opp-hz = /bits/ 64 <979200000>;
 240                         opp-microvolt = <905000 905000 1140000>;
 241                         opp-supported-hw = <0x70>;
 242                         clock-latency-ns = <200000>;
 243                 };
 244                 opp-1036800000 {
 245                         opp-hz = /bits/ 64 <1036800000>;
 246                         opp-microvolt = <905000 905000 1140000>;
 247                         opp-supported-hw = <0x7>;
 248                         clock-latency-ns = <200000>;
 249                 };
 250                 opp-1056000000 {
 251                         opp-hz = /bits/ 64 <1056000000>;
 252                         opp-microvolt = <905000 905000 1140000>;
 253                         opp-supported-hw = <0x70>;
 254                         clock-latency-ns = <200000>;
 255                 };
 256                 opp-1113600000 {
 257                         opp-hz = /bits/ 64 <1113600000>;
 258                         opp-microvolt = <905000 905000 1140000>;
 259                         opp-supported-hw = <0x7>;
 260                         clock-latency-ns = <200000>;
 261                 };
 262                 opp-1132800000 {
 263                         opp-hz = /bits/ 64 <1132800000>;
 264                         opp-microvolt = <905000 905000 1140000>;
 265                         opp-supported-hw = <0x70>;
 266                         clock-latency-ns = <200000>;
 267                 };
 268                 opp-1190400000 {
 269                         opp-hz = /bits/ 64 <1190400000>;
 270                         opp-microvolt = <905000 905000 1140000>;
 271                         opp-supported-hw = <0x7>;
 272                         clock-latency-ns = <200000>;
 273                 };
 274                 opp-1209600000 {
 275                         opp-hz = /bits/ 64 <1209600000>;
 276                         opp-microvolt = <905000 905000 1140000>;
 277                         opp-supported-hw = <0x70>;
 278                         clock-latency-ns = <200000>;
 279                 };
 280                 opp-1228800000 {
 281                         opp-hz = /bits/ 64 <1228800000>;
 282                         opp-microvolt = <905000 905000 1140000>;
 283                         opp-supported-hw = <0x7>;
 284                         clock-latency-ns = <200000>;
 285                 };
 286                 opp-1286400000 {
 287                         opp-hz = /bits/ 64 <1286400000>;
 288                         opp-microvolt = <1140000 905000 1140000>;
 289                         opp-supported-hw = <0x70>;
 290                         clock-latency-ns = <200000>;
 291                 };
 292                 opp-1324800000 {
 293                         opp-hz = /bits/ 64 <1324800000>;
 294                         opp-microvolt = <1140000 905000 1140000>;
 295                         opp-supported-hw = <0x5>;
 296                         clock-latency-ns = <200000>;
 297                 };
 298                 opp-1363200000 {
 299                         opp-hz = /bits/ 64 <1363200000>;
 300                         opp-microvolt = <1140000 905000 1140000>;
 301                         opp-supported-hw = <0x72>;
 302                         clock-latency-ns = <200000>;
 303                 };
 304                 opp-1401600000 {
 305                         opp-hz = /bits/ 64 <1401600000>;
 306                         opp-microvolt = <1140000 905000 1140000>;
 307                         opp-supported-hw = <0x5>;
 308                         clock-latency-ns = <200000>;
 309                 };
 310                 opp-1440000000 {
 311                         opp-hz = /bits/ 64 <1440000000>;
 312                         opp-microvolt = <1140000 905000 1140000>;
 313                         opp-supported-hw = <0x70>;
 314                         clock-latency-ns = <200000>;
 315                 };
 316                 opp-1478400000 {
 317                         opp-hz = /bits/ 64 <1478400000>;
 318                         opp-microvolt = <1140000 905000 1140000>;
 319                         opp-supported-hw = <0x1>;
 320                         clock-latency-ns = <200000>;
 321                 };
 322                 opp-1497600000 {
 323                         opp-hz = /bits/ 64 <1497600000>;
 324                         opp-microvolt = <1140000 905000 1140000>;
 325                         opp-supported-hw = <0x4>;
 326                         clock-latency-ns = <200000>;
 327                 };
 328                 opp-1516800000 {
 329                         opp-hz = /bits/ 64 <1516800000>;
 330                         opp-microvolt = <1140000 905000 1140000>;
 331                         opp-supported-hw = <0x70>;
 332                         clock-latency-ns = <200000>;
 333                 };
 334                 opp-1593600000 {
 335                         opp-hz = /bits/ 64 <1593600000>;
 336                         opp-microvolt = <1140000 905000 1140000>;
 337                         opp-supported-hw = <0x71>;
 338                         clock-latency-ns = <200000>;
 339                 };
 340                 opp-1996800000 {
 341                         opp-hz = /bits/ 64 <1996800000>;
 342                         opp-microvolt = <1140000 905000 1140000>;
 343                         opp-supported-hw = <0x20>;
 344                         clock-latency-ns = <200000>;
 345                 };
 346                 opp-2188800000 {
 347                         opp-hz = /bits/ 64 <2188800000>;
 348                         opp-microvolt = <1140000 905000 1140000>;
 349                         opp-supported-hw = <0x10>;
 350                         clock-latency-ns = <200000>;
 351                 };
 352         };
 353
 354         cluster1_opp: opp_table1 {
 355                 compatible = "operating-points-v2-kryo-cpu";
 356                 nvmem-cells = <&speedbin_efuse>;
 357                 opp-shared;
 358
 359                 opp-307200000 {
 360                         opp-hz = /bits/ 64 <307200000>;
 361                         opp-microvolt = <905000 905000 1140000>;
 362                         opp-supported-hw = <0x77>;
 363                         clock-latency-ns = <200000>;
 364                 };
 365                 opp-384000000 {
 366                         opp-hz = /bits/ 64 <384000000>;
 367                         opp-microvolt = <905000 905000 1140000>;
 368                         opp-supported-hw = <0x70>;
 369                         clock-latency-ns = <200000>;
 370                 };
 371                 opp-403200000 {
 372                         opp-hz = /bits/ 64 <403200000>;
 373                         opp-microvolt = <905000 905000 1140000>;
 374                         opp-supported-hw = <0x7>;
 375                         clock-latency-ns = <200000>;
 376                 };
 377                 opp-460800000 {
 378                         opp-hz = /bits/ 64 <460800000>;
 379                         opp-microvolt = <905000 905000 1140000>;
 380                         opp-supported-hw = <0x70>;
 381                         clock-latency-ns = <200000>;
 382                 };
 383                 opp-480000000 {
 384                         opp-hz = /bits/ 64 <480000000>;
 385                         opp-microvolt = <905000 905000 1140000>;
 386                         opp-supported-hw = <0x7>;
 387                         clock-latency-ns = <200000>;
 388                 };
 389                 opp-537600000 {
 390                         opp-hz = /bits/ 64 <537600000>;
 391                         opp-microvolt = <905000 905000 1140000>;
 392                         opp-supported-hw = <0x70>;
 393                         clock-latency-ns = <200000>;
 394                 };
 395                 opp-556800000 {
 396                         opp-hz = /bits/ 64 <556800000>;
 397                         opp-microvolt = <905000 905000 1140000>;
 398                         opp-supported-hw = <0x7>;
 399                         clock-latency-ns = <200000>;
 400                 };
 401                 opp-614400000 {
 402                         opp-hz = /bits/ 64 <614400000>;
 403                         opp-microvolt = <905000 905000 1140000>;
 404                         opp-supported-hw = <0x70>;
 405                         clock-latency-ns = <200000>;
 406                 };
 407                 opp-652800000 {
 408                         opp-hz = /bits/ 64 <652800000>;
 409                         opp-microvolt = <905000 905000 1140000>;
 410                         opp-supported-hw = <0x7>;
 411                         clock-latency-ns = <200000>;
 412                 };
 413                 opp-691200000 {
 414                         opp-hz = /bits/ 64 <691200000>;
 415                         opp-microvolt = <905000 905000 1140000>;
 416                         opp-supported-hw = <0x70>;
 417                         clock-latency-ns = <200000>;
 418                 };
 419                 opp-729600000 {
 420                         opp-hz = /bits/ 64 <729600000>;
 421                         opp-microvolt = <905000 905000 1140000>;
 422                         opp-supported-hw = <0x7>;
 423                         clock-latency-ns = <200000>;
 424                 };
 425                 opp-748800000 {
 426                         opp-hz = /bits/ 64 <748800000>;
 427                         opp-microvolt = <905000 905000 1140000>;
 428                         opp-supported-hw = <0x70>;
 429                         clock-latency-ns = <200000>;
 430                 };
 431                 opp-806400000 {
 432                         opp-hz = /bits/ 64 <806400000>;
 433                         opp-microvolt = <905000 905000 1140000>;
 434                         opp-supported-hw = <0x7>;
 435                         clock-latency-ns = <200000>;
 436                 };
 437                 opp-825600000 {
 438                         opp-hz = /bits/ 64 <825600000>;
 439                         opp-microvolt = <905000 905000 1140000>;
 440                         opp-supported-hw = <0x70>;
 441                         clock-latency-ns = <200000>;
 442                 };
 443                 opp-883200000 {
 444                         opp-hz = /bits/ 64 <883200000>;
 445                         opp-microvolt = <905000 905000 1140000>;
 446                         opp-supported-hw = <0x7>;
 447                         clock-latency-ns = <200000>;
 448                 };
 449                 opp-902400000 {
 450                         opp-hz = /bits/ 64 <902400000>;
 451                         opp-microvolt = <905000 905000 1140000>;
 452                         opp-supported-hw = <0x70>;
 453                         clock-latency-ns = <200000>;
 454                 };
 455                 opp-940800000 {
 456                         opp-hz = /bits/ 64 <940800000>;
 457                         opp-microvolt = <905000 905000 1140000>;
 458                         opp-supported-hw = <0x7>;
 459                         clock-latency-ns = <200000>;
 460                 };
 461                 opp-979200000 {
 462                         opp-hz = /bits/ 64 <979200000>;
 463                         opp-microvolt = <905000 905000 1140000>;
 464                         opp-supported-hw = <0x70>;
 465                         clock-latency-ns = <200000>;
 466                 };
 467                 opp-1036800000 {
 468                         opp-hz = /bits/ 64 <1036800000>;
 469                         opp-microvolt = <905000 905000 1140000>;
 470                         opp-supported-hw = <0x7>;
 471                         clock-latency-ns = <200000>;
 472                 };
 473                 opp-1056000000 {
 474                         opp-hz = /bits/ 64 <1056000000>;
 475                         opp-microvolt = <905000 905000 1140000>;
 476                         opp-supported-hw = <0x70>;
 477                         clock-latency-ns = <200000>;
 478                 };
 479                 opp-1113600000 {
 480                         opp-hz = /bits/ 64 <1113600000>;
 481                         opp-microvolt = <905000 905000 1140000>;
 482                         opp-supported-hw = <0x7>;
 483                         clock-latency-ns = <200000>;
 484                 };
 485                 opp-1132800000 {
 486                         opp-hz = /bits/ 64 <1132800000>;
 487                         opp-microvolt = <905000 905000 1140000>;
 488                         opp-supported-hw = <0x70>;
 489                         clock-latency-ns = <200000>;
 490                 };
 491                 opp-1190400000 {
 492                         opp-hz = /bits/ 64 <1190400000>;
 493                         opp-microvolt = <905000 905000 1140000>;
 494                         opp-supported-hw = <0x7>;
 495                         clock-latency-ns = <200000>;
 496                 };
 497                 opp-1209600000 {
 498                         opp-hz = /bits/ 64 <1209600000>;
 499                         opp-microvolt = <905000 905000 1140000>;
 500                         opp-supported-hw = <0x70>;
 501                         clock-latency-ns = <200000>;
 502                 };
 503                 opp-1248000000 {
 504                         opp-hz = /bits/ 64 <1248000000>;
 505                         opp-microvolt = <905000 905000 1140000>;
 506                         opp-supported-hw = <0x7>;
 507                         clock-latency-ns = <200000>;
 508                 };
 509                 opp-1286400000 {
 510                         opp-hz = /bits/ 64 <1286400000>;
 511                         opp-microvolt = <905000 905000 1140000>;
 512                         opp-supported-hw = <0x70>;
 513                         clock-latency-ns = <200000>;
 514                 };
 515                 opp-1324800000 {
 516                         opp-hz = /bits/ 64 <1324800000>;
 517                         opp-microvolt = <1140000 905000 1140000>;
 518                         opp-supported-hw = <0x7>;
 519                         clock-latency-ns = <200000>;
 520                 };
 521                 opp-1363200000 {
 522                         opp-hz = /bits/ 64 <1363200000>;
 523                         opp-microvolt = <1140000 905000 1140000>;
 524                         opp-supported-hw = <0x70>;
 525                         clock-latency-ns = <200000>;
 526                 };
 527                 opp-1401600000 {
 528                         opp-hz = /bits/ 64 <1401600000>;
 529                         opp-microvolt = <1140000 905000 1140000>;
 530                         opp-supported-hw = <0x7>;
 531                         clock-latency-ns = <200000>;
 532                 };
 533                 opp-1440000000 {
 534                         opp-hz = /bits/ 64 <1440000000>;
 535                         opp-microvolt = <1140000 905000 1140000>;
 536                         opp-supported-hw = <0x70>;
 537                         clock-latency-ns = <200000>;
 538                 };
 539                 opp-1478400000 {
 540                         opp-hz = /bits/ 64 <1478400000>;
 541                         opp-microvolt = <1140000 905000 1140000>;
 542                         opp-supported-hw = <0x7>;
 543                         clock-latency-ns = <200000>;
 544                 };
 545                 opp-1516800000 {
 546                         opp-hz = /bits/ 64 <1516800000>;
 547                         opp-microvolt = <1140000 905000 1140000>;
 548                         opp-supported-hw = <0x70>;
 549                         clock-latency-ns = <200000>;
 550                 };
 551                 opp-1555200000 {
 552                         opp-hz = /bits/ 64 <1555200000>;
 553                         opp-microvolt = <1140000 905000 1140000>;
 554                         opp-supported-hw = <0x7>;
 555                         clock-latency-ns = <200000>;
 556                 };
 557                 opp-1593600000 {
 558                         opp-hz = /bits/ 64 <1593600000>;
 559                         opp-microvolt = <1140000 905000 1140000>;
 560                         opp-supported-hw = <0x70>;
 561                         clock-latency-ns = <200000>;
 562                 };
 563                 opp-1632000000 {
 564                         opp-hz = /bits/ 64 <1632000000>;
 565                         opp-microvolt = <1140000 905000 1140000>;
 566                         opp-supported-hw = <0x7>;
 567                         clock-latency-ns = <200000>;
 568                 };
 569                 opp-1670400000 {
 570                         opp-hz = /bits/ 64 <1670400000>;
 571                         opp-microvolt = <1140000 905000 1140000>;
 572                         opp-supported-hw = <0x70>;
 573                         clock-latency-ns = <200000>;
 574                 };
 575                 opp-1708800000 {
 576                         opp-hz = /bits/ 64 <1708800000>;
 577                         opp-microvolt = <1140000 905000 1140000>;
 578                         opp-supported-hw = <0x7>;
 579                         clock-latency-ns = <200000>;
 580                 };
 581                 opp-1747200000 {
 582                         opp-hz = /bits/ 64 <1747200000>;
 583                         opp-microvolt = <1140000 905000 1140000>;
 584                         opp-supported-hw = <0x70>;
 585                         clock-latency-ns = <200000>;
 586                 };
 587                 opp-1785600000 {
 588                         opp-hz = /bits/ 64 <1785600000>;
 589                         opp-microvolt = <1140000 905000 1140000>;
 590                         opp-supported-hw = <0x7>;
 591                         clock-latency-ns = <200000>;
 592                 };
 593                 opp-1804800000 {
 594                         opp-hz = /bits/ 64 <1804800000>;
 595                         opp-microvolt = <1140000 905000 1140000>;
 596                         opp-supported-hw = <0x6>;
 597                         clock-latency-ns = <200000>;
 598                 };
 599                 opp-1824000000 {
 600                         opp-hz = /bits/ 64 <1824000000>;
 601                         opp-microvolt = <1140000 905000 1140000>;
 602                         opp-supported-hw = <0x71>;
 603                         clock-latency-ns = <200000>;
 604                 };
 605                 opp-1900800000 {
 606                         opp-hz = /bits/ 64 <1900800000>;
 607                         opp-microvolt = <1140000 905000 1140000>;
 608                         opp-supported-hw = <0x74>;
 609                         clock-latency-ns = <200000>;
 610                 };
 611                 opp-1920000000 {
 612                         opp-hz = /bits/ 64 <1920000000>;
 613                         opp-microvolt = <1140000 905000 1140000>;
 614                         opp-supported-hw = <0x1>;
 615                         clock-latency-ns = <200000>;
 616                 };
 617                 opp-1977600000 {
 618                         opp-hz = /bits/ 64 <1977600000>;
 619                         opp-microvolt = <1140000 905000 1140000>;
 620                         opp-supported-hw = <0x30>;
 621                         clock-latency-ns = <200000>;
 622                 };
 623                 opp-1996800000 {
 624                         opp-hz = /bits/ 64 <1996800000>;
 625                         opp-microvolt = <1140000 905000 1140000>;
 626                         opp-supported-hw = <0x1>;
 627                         clock-latency-ns = <200000>;
 628                 };
 629                 opp-2054400000 {
 630                         opp-hz = /bits/ 64 <2054400000>;
 631                         opp-microvolt = <1140000 905000 1140000>;
 632                         opp-supported-hw = <0x30>;
 633                         clock-latency-ns = <200000>;
 634                 };
 635                 opp-2073600000 {
 636                         opp-hz = /bits/ 64 <2073600000>;
 637                         opp-microvolt = <1140000 905000 1140000>;
 638                         opp-supported-hw = <0x1>;
 639                         clock-latency-ns = <200000>;
 640                 };
 641                 opp-2150400000 {
 642                         opp-hz = /bits/ 64 <2150400000>;
 643                         opp-microvolt = <1140000 905000 1140000>;
 644                         opp-supported-hw = <0x31>;
 645                         clock-latency-ns = <200000>;
 646                 };
 647                 opp-2246400000 {
 648                         opp-hz = /bits/ 64 <2246400000>;
 649                         opp-microvolt = <1140000 905000 1140000>;
 650                         opp-supported-hw = <0x10>;
 651                         clock-latency-ns = <200000>;
 652                 };
 653                 opp-2342400000 {
 654                         opp-hz = /bits/ 64 <2342400000>;
 655                         opp-microvolt = <1140000 905000 1140000>;
 656                         opp-supported-hw = <0x10>;
 657                         clock-latency-ns = <200000>;
 658                 };
 659         };
 660
 661 ....
 662
 663 reserved-memory {
 664         #address-cells = <2>;
 665         #size-cells = <2>;
 666         ranges;
 667 ....
 668         smem_mem: smem-mem@86000000 {
 669                 reg = <0x0 0x86000000 0x0 0x200000>;
 670                 no-map;
 671         };
 672 ....
 673 };
 674
 675 smem {
 676         compatible = "qcom,smem";
 677         memory-region = <&smem_mem>;
 678         hwlocks = <&tcsr_mutex 3>;
 679 };
 680
 681 soc {
 682 ....
 683         qfprom: qfprom@74000 {
 684                 compatible = "qcom,qfprom";
 685                 reg = <0x00074000 0x8ff>;
 686                 #address-cells = <1>;
 687                 #size-cells = <1>;
 688                 ....
 689                 speedbin_efuse: speedbin@133 {
 690                         reg = <0x133 0x1>;
 691                         bits = <5 3>;
 692                 };
 693         };
 694 };
 695
 696 Example 2:
 697 ---------
 698
 699         cpus {
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702
 703                 CPU0: cpu@100 {
 704                         device_type = "cpu";
 705                         compatible = "arm,cortex-a53";
 706                         reg = <0x100>;
 707                         ....
 708                         clocks = <&apcs_glb>;
 709                         operating-points-v2 = <&cpu_opp_table>;
 710                         power-domains = <&cpr>;
 711                         power-domain-names = "cpr";
 712                 };
 713
 714                 CPU1: cpu@101 {
 715                         device_type = "cpu";
 716                         compatible = "arm,cortex-a53";
 717                         reg = <0x101>;
 718                         ....
 719                         clocks = <&apcs_glb>;
 720                         operating-points-v2 = <&cpu_opp_table>;
 721                         power-domains = <&cpr>;
 722                         power-domain-names = "cpr";
 723                 };
 724
 725                 CPU2: cpu@102 {
 726                         device_type = "cpu";
 727                         compatible = "arm,cortex-a53";
 728                         reg = <0x102>;
 729                         ....
 730                         clocks = <&apcs_glb>;
 731                         operating-points-v2 = <&cpu_opp_table>;
 732                         power-domains = <&cpr>;
 733                         power-domain-names = "cpr";
 734                 };
 735
 736                 CPU3: cpu@103 {
 737                         device_type = "cpu";
 738                         compatible = "arm,cortex-a53";
 739                         reg = <0x103>;
 740                         ....
 741                         clocks = <&apcs_glb>;
 742                         operating-points-v2 = <&cpu_opp_table>;
 743                         power-domains = <&cpr>;
 744                         power-domain-names = "cpr";
 745                 };
 746         };
 747
 748         cpu_opp_table: cpu-opp-table {
 749                 compatible = "operating-points-v2-kryo-cpu";
 750                 opp-shared;
 751
 752                 opp-1094400000 {
 753                         opp-hz = /bits/ 64 <1094400000>;
 754                         required-opps = <&cpr_opp1>;
 755                 };
 756                 opp-1248000000 {
 757                         opp-hz = /bits/ 64 <1248000000>;
 758                         required-opps = <&cpr_opp2>;
 759                 };
 760                 opp-1401600000 {
 761                         opp-hz = /bits/ 64 <1401600000>;
 762                         required-opps = <&cpr_opp3>;
 763                 };
 764         };
 765
 766         cpr_opp_table: cpr-opp-table {
 767                 compatible = "operating-points-v2-qcom-level";
 768
 769                 cpr_opp1: opp1 {
 770                         opp-level = <1>;
 771                         qcom,opp-fuse-level = <1>;
 772                 };
 773                 cpr_opp2: opp2 {
 774                         opp-level = <2>;
 775                         qcom,opp-fuse-level = <2>;
 776                 };
 777                 cpr_opp3: opp3 {
 778                         opp-level = <3>;
 779                         qcom,opp-fuse-level = <3>;
 780                 };
 781         };
 782
 783 ....
 784
 785 soc {
 786 ....
 787         cpr: power-controller@b018000 {
 788                 compatible = "qcom,qcs404-cpr", "qcom,cpr";
 789                 reg = <0x0b018000 0x1000>;
 790                 ....
 791                 vdd-apc-supply = <&pms405_s3>;
 792                 #power-domain-cells = <0>;
 793                 operating-points-v2 = <&cpr_opp_table>;
 794                 ....
 795         };
 796 };