Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: The TI AM654x/J721E/AM642x SoC Gigabit Ethernet MAC (Media Access Controller)
   8
   9 maintainers:
  10   - Siddharth Vadapalli <s-vadapalli@ti.com>
  11   - Ravi Gunasekaran <r-gunasekaran@ti.com>
  12   - Roger Quadros <rogerq@kernel.org>
  13
  14 description:
  15   The TI AM654x/J721E SoC Gigabit Ethernet MAC (CPSW2G NUSS) has two ports
  16   (one external) and provides Ethernet packet communication for the device.
  17   The TI AM642x SoC Gigabit Ethernet MAC (CPSW3G NUSS) has three ports
  18   (two external) and provides Ethernet packet communication and switching.
  19
  20   The internal Communications Port Programming Interface (CPPI5) (Host port 0).
  21   Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
  22   and one RX channels and operating by NAVSS Unified DMA  Peripheral Root
  23   Complex (UDMA-P) controller.
  24
  25   CPSWxG features
  26   updated Address Lookup Engine (ALE).
  27   priority level Quality Of Service (QOS) support (802.1p)
  28   Support for Audio/Video Bridging (P802.1Qav/D6.0)
  29   Support for IEEE 1588 Clock Synchronization (2008 Annex D, Annex E and Annex F)
  30   Flow Control (802.3x) Support
  31   Time Sensitive Network Support
  32   IEEE P902.3br/D2.0 Interspersing Express Traffic
  33   IEEE 802.1Qbv/D2.2 Enhancements for Scheduled Traffic
  34   Configurable number of addresses plus VLANs
  35   Configurable number of classifier/policers
  36   VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
  37   ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
  38   RX/TX csum offload
  39   Management Data Input/Output (MDIO) interface for PHYs management
  40   RMII/RGMII Interfaces support
  41   new version of Common Platform Time Sync (CPTS)
  42
  43   The CPSWxG NUSS is integrated into
  44     device MCU domain named MCU_CPSW0 on AM654x/J721E SoC.
  45     device MAIN domain named CPSW0 on AM642x SoC.
  46
  47   Specifications can be found at
  48     https://www.ti.com/lit/pdf/spruid7
  49     https://www.ti.com/lit/zip/spruil1
  50     https://www.ti.com/lit/pdf/spruim2
  51
  52 properties:
  53   "#address-cells": true
  54   "#size-cells": true
  55
  56   compatible:
  57     enum:
  58       - ti,am642-cpsw-nuss
  59       - ti,am654-cpsw-nuss
  60       - ti,j7200-cpswxg-nuss
  61       - ti,j721e-cpsw-nuss
  62       - ti,j721e-cpswxg-nuss
  63       - ti,j784s4-cpswxg-nuss
  64
  65   reg:
  66     maxItems: 1
  67     description:
  68       The physical base address and size of full the CPSWxG NUSS IO range
  69
  70   reg-names:
  71     items:
  72       - const: cpsw_nuss
  73
  74   ranges: true
  75
  76   dma-coherent: true
  77
  78   clocks:
  79     maxItems: 1
  80     description: CPSWxG NUSS functional clock
  81
  82   clock-names:
  83     items:
  84       - const: fck
  85
  86   assigned-clock-parents: true
  87
  88   assigned-clocks: true
  89
  90   power-domains:
  91     maxItems: 1
  92
  93   dmas:
  94     maxItems: 9
  95
  96   dma-names:
  97     items:
  98       - const: tx0
  99       - const: tx1
 100       - const: tx2
 101       - const: tx3
 102       - const: tx4
 103       - const: tx5
 104       - const: tx6
 105       - const: tx7
 106       - const: rx
 107
 108   ethernet-ports:
 109     type: object
 110     properties:
 111       '#address-cells':
 112         const: 1
 113       '#size-cells':
 114         const: 0
 115
 116     patternProperties:
 117       "^port@[1-8]$":
 118         type: object
 119         description: CPSWxG NUSS external ports
 120
 121         $ref: ethernet-controller.yaml#
 122         unevaluatedProperties: false
 123
 124         properties:
 125           reg:
 126             minimum: 1
 127             maximum: 8
 128             description: CPSW port number
 129
 130           phys:
 131             minItems: 1
 132             items:
 133               - description: CPSW MAC's PHY.
 134               - description: Serdes PHY. Serdes PHY is required only if
 135                              the Serdes has to be configured in the
 136                              Single-Link configuration.
 137
 138           phy-names:
 139             minItems: 1
 140             items:
 141               - const: mac
 142               - const: serdes
 143
 144           label:
 145             description: label associated with this port
 146
 147           ti,mac-only:
 148             $ref: /schemas/types.yaml#/definitions/flag
 149             description:
 150               Specifies the port works in mac-only mode.
 151
 152           ti,syscon-efuse:
 153             $ref: /schemas/types.yaml#/definitions/phandle-array
 154             items:
 155               - items:
 156                   - description: Phandle to the system control device node which
 157                       provides access to efuse
 158                   - description: offset to efuse registers???
 159             description:
 160               Phandle to the system control device node which provides access
 161               to efuse IO range with MAC addresses
 162
 163         required:
 164           - reg
 165           - phys
 166
 167     additionalProperties: false
 168
 169 patternProperties:
 170   "^mdio@[0-9a-f]+$":
 171     type: object
 172     $ref: ti,davinci-mdio.yaml#
 173
 174     description:
 175       CPSW MDIO bus.
 176
 177   "^cpts@[0-9a-f]+":
 178     type: object
 179     $ref: ti,k3-am654-cpts.yaml#
 180     description:
 181       CPSW Common Platform Time Sync (CPTS) module.
 182
 183 required:
 184   - compatible
 185   - reg
 186   - reg-names
 187   - ranges
 188   - clocks
 189   - clock-names
 190   - power-domains
 191   - dmas
 192   - dma-names
 193   - '#address-cells'
 194   - '#size-cells'
 195
 196 allOf:
 197   - if:
 198       not:
 199         properties:
 200           compatible:
 201             contains:
 202               enum:
 203                 - ti,j721e-cpswxg-nuss
 204                 - ti,j784s4-cpswxg-nuss
 205     then:
 206       properties:
 207         ethernet-ports:
 208           patternProperties:
 209             "^port@[5-8]$": false
 210             "^port@[1-4]$":
 211               properties:
 212                 reg:
 213                   minimum: 1
 214                   maximum: 4
 215
 216   - if:
 217       not:
 218         properties:
 219           compatible:
 220             contains:
 221               enum:
 222                 - ti,j7200-cpswxg-nuss
 223                 - ti,j721e-cpswxg-nuss
 224                 - ti,j784s4-cpswxg-nuss
 225     then:
 226       properties:
 227         ethernet-ports:
 228           patternProperties:
 229             "^port@[3-8]$": false
 230             "^port@[1-2]$":
 231               properties:
 232                 reg:
 233                   minimum: 1
 234                   maximum: 2
 235
 236 additionalProperties: false
 237
 238 examples:
 239   - |
 240     #include <dt-bindings/soc/ti,sci_pm_domain.h>
 241     #include <dt-bindings/net/ti-dp83867.h>
 242     #include <dt-bindings/interrupt-controller/irq.h>
 243     #include <dt-bindings/interrupt-controller/arm-gic.h>
 244
 245     bus {
 246         #address-cells = <2>;
 247         #size-cells = <2>;
 248
 249         mcu_cpsw: ethernet@46000000 {
 250             compatible = "ti,am654-cpsw-nuss";
 251             #address-cells = <2>;
 252             #size-cells = <2>;
 253             reg = <0x0 0x46000000 0x0 0x200000>;
 254             reg-names = "cpsw_nuss";
 255             ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
 256             dma-coherent;
 257             clocks = <&k3_clks 5 10>;
 258             clock-names = "fck";
 259             power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
 260             pinctrl-names = "default";
 261             pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
 262
 263             dmas = <&mcu_udmap 0xf000>,
 264                    <&mcu_udmap 0xf001>,
 265                    <&mcu_udmap 0xf002>,
 266                    <&mcu_udmap 0xf003>,
 267                    <&mcu_udmap 0xf004>,
 268                    <&mcu_udmap 0xf005>,
 269                    <&mcu_udmap 0xf006>,
 270                    <&mcu_udmap 0xf007>,
 271                    <&mcu_udmap 0x7000>;
 272             dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
 273                         "rx";
 274
 275             ethernet-ports {
 276                 #address-cells = <1>;
 277                 #size-cells = <0>;
 278
 279                 cpsw_port1: port@1 {
 280                     reg = <1>;
 281                     ti,mac-only;
 282                     label = "port1";
 283                     ti,syscon-efuse = <&mcu_conf 0x200>;
 284                     phys = <&phy_gmii_sel 1>;
 285
 286                     phy-mode = "rgmii-rxid";
 287                     phy-handle = <&phy0>;
 288                 };
 289             };
 290
 291             davinci_mdio: mdio@f00 {
 292                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
 293                 reg = <0x0 0xf00 0x0 0x100>;
 294                 #address-cells = <1>;
 295                 #size-cells = <0>;
 296                 clocks = <&k3_clks 5 10>;
 297                 clock-names = "fck";
 298                 bus_freq = <1000000>;
 299
 300                 phy0: ethernet-phy@0 {
 301                     reg = <0>;
 302                     ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 303                     ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
 304                 };
 305             };
 306         };
 307
 308         cpts@3d000 {
 309              compatible = "ti,am65-cpts";
 310              reg = <0x0 0x3d000 0x0 0x400>;
 311              clocks = <&k3_clks 18 2>;
 312              clock-names = "cpts";
 313              interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
 314              interrupt-names = "cpts";
 315              ti,cpts-ext-ts-inputs = <4>;
 316              ti,cpts-periodic-outputs = <2>;
 317         };
 318     };