Documentation/devicetree/bindings/net/stm32-dwmac.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright 2019 BayLibre, SAS
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
   9
  10 maintainers:
  11   - Alexandre Torgue <alexandre.torgue@st.com>
  12   - Christophe Roullier <christophe.roullier@st.com>
  13
  14 description:
  15   This file documents platform glue layer for stmmac.
  16
  17 # We need a select here so we don't match all nodes with 'snps,dwmac'
  18 select:
  19   properties:
  20     compatible:
  21       contains:
  22         enum:
  23           - st,stm32-dwmac
  24           - st,stm32mp1-dwmac
  25   required:
  26     - compatible
  27
  28 allOf:
  29   - $ref: "snps,dwmac.yaml#"
  30
  31 properties:
  32   compatible:
  33     oneOf:
  34       - items:
  35           - enum:
  36               - st,stm32mp1-dwmac
  37           - const: snps,dwmac-4.20a
  38       - items:
  39           - enum:
  40               - st,stm32-dwmac
  41           - const: snps,dwmac-4.10a
  42       - items:
  43           - enum:
  44               - st,stm32-dwmac
  45           - const: snps,dwmac-3.50a
  46
  47   clocks:
  48     minItems: 3
  49     maxItems: 6
  50     items:
  51       - description: GMAC main clock
  52       - description: MAC TX clock
  53       - description: MAC RX clock
  54       - description: For MPU family, used for power mode
  55       - description: For MPU family, used for PHY without quartz
  56       - description: PTP clock
  57
  58   clock-names:
  59     minItems: 3
  60     maxItems: 6
  61     contains:
  62       enum:
  63         - stmmaceth
  64         - mac-clk-tx
  65         - mac-clk-rx
  66         - ethstp
  67         - eth-ck
  68         - ptp_ref
  69
  70   st,syscon:
  71     $ref: "/schemas/types.yaml#/definitions/phandle-array"
  72     description:
  73       Should be phandle/offset pair. The phandle to the syscon node which
  74       encompases the glue register, and the offset of the control register
  75
  76   st,eth-clk-sel:
  77     description:
  78       set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
  79     type: boolean
  80
  81   st,eth-ref-clk-sel:
  82     description:
  83       set this property in RMII mode when you have PHY without crystal 50MHz and want to
  84       select RCC clock instead of ETH_REF_CLK.
  85     type: boolean
  86
  87 required:
  88   - compatible
  89   - clocks
  90   - clock-names
  91   - st,syscon
  92
  93 unevaluatedProperties: false
  94
  95 examples:
  96   - |
  97     #include <dt-bindings/interrupt-controller/arm-gic.h>
  98     #include <dt-bindings/clock/stm32mp1-clks.h>
  99     #include <dt-bindings/reset/stm32mp1-resets.h>
 100     #include <dt-bindings/mfd/stm32h7-rcc.h>
 101     //Example 1
 102      ethernet0: ethernet@5800a000 {
 103            compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
 104            reg = <0x5800a000 0x2000>;
 105            reg-names = "stmmaceth";
 106            interrupts = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 107            interrupt-names = "macirq";
 108            clock-names = "stmmaceth",
 109                      "mac-clk-tx",
 110                      "mac-clk-rx",
 111                      "ethstp",
 112                      "eth-ck";
 113            clocks = <&rcc ETHMAC>,
 114                 <&rcc ETHTX>,
 115                 <&rcc ETHRX>,
 116                 <&rcc ETHSTP>,
 117                 <&rcc ETHCK_K>;
 118            st,syscon = <&syscfg 0x4>;
 119            snps,pbl = <2>;
 120            snps,axi-config = <&stmmac_axi_config_0>;
 121            snps,tso;
 122            phy-mode = "rgmii";
 123        };
 124
 125     //Example 2 (MCU example)
 126      ethernet1: ethernet@40028000 {
 127            compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 128            reg = <0x40028000 0x8000>;
 129            reg-names = "stmmaceth";
 130            interrupts = <0 61 0>, <0 62 0>;
 131            interrupt-names = "macirq", "eth_wake_irq";
 132            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 133            clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
 134            st,syscon = <&syscfg 0x4>;
 135            snps,pbl = <8>;
 136            snps,mixed-burst;
 137            phy-mode = "mii";
 138        };
 139
 140     //Example 3
 141      ethernet2: ethernet@40027000 {
 142            compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 143            reg = <0x40028000 0x8000>;
 144            reg-names = "stmmaceth";
 145            interrupts = <61>;
 146            interrupt-names = "macirq";
 147            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 148            clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
 149            st,syscon = <&syscfg 0x4>;
 150            snps,pbl = <8>;
 151            phy-mode = "mii";
 152        };