Documentation/devicetree/bindings/net/stm32-dwmac.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright 2019 BayLibre, SAS
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/net/stm32-dwmac.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: STMicroelectronics STM32 / MCU DWMAC glue layer controller
   9
  10 maintainers:
  11   - Alexandre Torgue <alexandre.torgue@st.com>
  12   - Christophe Roullier <christophe.roullier@st.com>
  13
  14 description:
  15   This file documents platform glue layer for stmmac.
  16
  17 # We need a select here so we don't match all nodes with 'snps,dwmac'
  18 select:
  19   properties:
  20     compatible:
  21       contains:
  22         enum:
  23           - st,stm32-dwmac
  24           - st,stm32mp1-dwmac
  25   required:
  26     - compatible
  27
  28 allOf:
  29   - $ref: "snps,dwmac.yaml#"
  30
  31 properties:
  32   compatible:
  33     oneOf:
  34       - items:
  35           - enum:
  36               - st,stm32mp1-dwmac
  37           - const: snps,dwmac-4.20a
  38       - items:
  39           - enum:
  40               - st,stm32-dwmac
  41           - const: snps,dwmac-4.10a
  42       - items:
  43           - enum:
  44               - st,stm32-dwmac
  45           - const: snps,dwmac-3.50a
  46
  47   clocks:
  48     minItems: 3
  49     maxItems: 5
  50     items:
  51         - description: GMAC main clock
  52         - description: MAC TX clock
  53         - description: MAC RX clock
  54         - description: For MPU family, used for power mode
  55         - description: For MPU family, used for PHY without quartz
  56
  57   clock-names:
  58     minItems: 3
  59     maxItems: 5
  60     contains:
  61       enum:
  62         - stmmaceth
  63         - mac-clk-tx
  64         - mac-clk-rx
  65         - ethstp
  66         - eth-ck
  67
  68   st,syscon:
  69     $ref: "/schemas/types.yaml#/definitions/phandle-array"
  70     description:
  71       Should be phandle/offset pair. The phandle to the syscon node which
  72       encompases the glue register, and the offset of the control register
  73
  74   st,eth-clk-sel:
  75     description:
  76       set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125.
  77     type: boolean
  78
  79   st,eth-ref-clk-sel:
  80     description:
  81       set this property in RMII mode when you have PHY without crystal 50MHz and want to
  82       select RCC clock instead of ETH_REF_CLK.
  83     type: boolean
  84
  85 required:
  86   - compatible
  87   - clocks
  88   - clock-names
  89   - st,syscon
  90
  91 examples:
  92  - |
  93     #include <dt-bindings/interrupt-controller/arm-gic.h>
  94     #include <dt-bindings/clock/stm32mp1-clks.h>
  95     #include <dt-bindings/reset/stm32mp1-resets.h>
  96     #include <dt-bindings/mfd/stm32h7-rcc.h>
  97     //Example 1
  98      ethernet0: ethernet@5800a000 {
  99            compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
 100            reg = <0x5800a000 0x2000>;
 101            reg-names = "stmmaceth";
 102            interrupts = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 103            interrupt-names = "macirq";
 104            clock-names = "stmmaceth",
 105                      "mac-clk-tx",
 106                      "mac-clk-rx",
 107                      "ethstp",
 108                      "eth-ck";
 109            clocks = <&rcc ETHMAC>,
 110                 <&rcc ETHTX>,
 111                 <&rcc ETHRX>,
 112                 <&rcc ETHSTP>,
 113                 <&rcc ETHCK_K>;
 114            st,syscon = <&syscfg 0x4>;
 115            snps,pbl = <2>;
 116            snps,axi-config = <&stmmac_axi_config_0>;
 117            snps,tso;
 118            phy-mode = "rgmii";
 119        };
 120
 121     //Example 2 (MCU example)
 122      ethernet1: ethernet@40028000 {
 123            compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 124            reg = <0x40028000 0x8000>;
 125            reg-names = "stmmaceth";
 126            interrupts = <0 61 0>, <0 62 0>;
 127            interrupt-names = "macirq", "eth_wake_irq";
 128            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 129            clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
 130            st,syscon = <&syscfg 0x4>;
 131            snps,pbl = <8>;
 132            snps,mixed-burst;
 133            phy-mode = "mii";
 134        };
 135
 136     //Example 3
 137      ethernet2: ethernet@40027000 {
 138            compatible = "st,stm32-dwmac", "snps,dwmac-4.10a";
 139            reg = <0x40028000 0x8000>;
 140            reg-names = "stmmaceth";
 141            interrupts = <61>;
 142            interrupt-names = "macirq";
 143            clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 144            clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
 145            st,syscon = <&syscfg 0x4>;
 146            snps,pbl = <8>;
 147            phy-mode = "mii";
 148        };