1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC Device Tree Bindings
10 - Alexandre Torgue <alexandre.torgue@st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
14 # Select every compatible, including the deprecated ones. This way, we
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
17 # as a valid value in the compatible property description
41 # We need to include all the compatibles from schemas that will
42 # include that schemas, otherwise compatible won't validate for
47 - allwinner,sun7i-a20-gmac
48 - allwinner,sun8i-a83t-emac
49 - allwinner,sun8i-h3-emac
50 - allwinner,sun8i-r40-emac
51 - allwinner,sun8i-v3s-emac
52 - allwinner,sun50i-a64-emac
70 - description: Combined signal for various interrupt events
71 - description: The interrupt to manage the remote wake-up packet detection
72 - description: The interrupt that occurs when Rx exits the LPI state
86 - description: GMAC main clock
87 - description: Peripheral registers interface clock
89 PTP reference clock. This clock is used for programming the
90 Timestamp Addend Register. If not passed then the system
91 clock will be used and this is fine on some platforms.
110 $ref: /schemas/types.yaml#definitions/phandle
112 AXI BUS Mode parameters. Phandle to a node that can contain the
114 * snps,lpi_en, enable Low Power Interface
115 * snps,xit_frm, unlock on WoL
116 * snps,wr_osr_lmt, max write outstanding req. limit
117 * snps,rd_osr_lmt, max read outstanding req. limit
118 * snps,kbbe, do not cross 1KiB boundary.
119 * snps,blen, this is a vector of supported burst length.
120 * snps,fb, fixed-burst
121 * snps,mb, mixed-burst
122 * snps,rb, rebuild INCRx Burst
125 $ref: /schemas/types.yaml#definitions/phandle
127 Multiple RX Queues parameters. Phandle to a node that can
128 contain the following properties
129 * snps,rx-queues-to-use, number of RX queues to be used in the
131 * Choose one of these RX scheduling algorithms
132 * snps,rx-sched-sp, Strict priority
133 * snps,rx-sched-wsp, Weighted Strict priority
135 * Choose one of these modes
136 * snps,dcb-algorithm, Queue to be enabled as DCB
137 * snps,avb-algorithm, Queue to be enabled as AVB
138 * snps,map-to-dma-channel, Channel to map
139 * Specifiy specific packet routing
140 * snps,route-avcp, AV Untagged Control packets
141 * snps,route-ptp, PTP Packets
142 * snps,route-dcbcp, DCB Control Packets
143 * snps,route-up, Untagged Packets
144 * snps,route-multi-broad, Multicast & Broadcast Packets
145 * snps,priority, RX queue priority (Range 0x0 to 0xF)
148 $ref: /schemas/types.yaml#definitions/phandle
150 Multiple TX Queues parameters. Phandle to a node that can
151 contain the following properties
152 * snps,tx-queues-to-use, number of TX queues to be used in the
154 * Choose one of these TX scheduling algorithms
155 * snps,tx-sched-wrr, Weighted Round Robin
156 * snps,tx-sched-wfq, Weighted Fair Queuing
157 * snps,tx-sched-dwrr, Deficit Weighted Round Robin
158 * snps,tx-sched-sp, Strict priority
160 * snps,weight, TX queue weight (if using a DCB weight
162 * Choose one of these modes
163 * snps,dcb-algorithm, TX queue will be working in DCB
164 * snps,avb-algorithm, TX queue will be working in AVB
165 [Attention] Queue 0 is reserved for legacy traffic
166 and so no AVB is available in this queue.
167 * Configure Credit Base Shaper (if AVB Mode selected)
168 * snps,send_slope, enable Low Power Interface
169 * snps,idle_slope, unlock on WoL
170 * snps,high_credit, max write outstanding req. limit
171 * snps,low_credit, max read outstanding req. limit
172 * snps,priority, TX queue priority (Range 0x0 to 0xF)
180 snps,reset-active-low:
182 $ref: /schemas/types.yaml#definitions/flag
184 Indicates that the PHY Reset is active low
186 snps,reset-delays-us:
189 - $ref: /schemas/types.yaml#definitions/uint32-array
193 Triplet of delays. The 1st cell is reset pre-delay in micro
194 seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
195 cell is reset post-delay in micro seconds.
198 $ref: /schemas/types.yaml#definitions/flag
200 Use Address-Aligned Beats
203 $ref: /schemas/types.yaml#definitions/flag
205 Program the DMA to use the fixed burst mode
208 $ref: /schemas/types.yaml#definitions/flag
210 Program the DMA to use the mixed burst mode
212 snps,force_thresh_dma_mode:
213 $ref: /schemas/types.yaml#definitions/flag
215 Force DMA to use the threshold mode for both tx and rx
217 snps,force_sf_dma_mode:
218 $ref: /schemas/types.yaml#definitions/flag
220 Force DMA to use the Store and Forward mode for both tx and
221 rx. This flag is ignored if force_thresh_dma_mode is set.
223 snps,en-tx-lpi-clockgating:
224 $ref: /schemas/types.yaml#definitions/flag
226 Enable gating of the MAC TX clock during TX low-power mode
228 snps,multicast-filter-bins:
229 $ref: /schemas/types.yaml#definitions/uint32
231 Number of multicast filter hash bins supported by this device
234 snps,perfect-filter-entries:
235 $ref: /schemas/types.yaml#definitions/uint32
237 Number of perfect filter entries supported by this device
241 $ref: /schemas/types.yaml#definitions/uint32
243 Port selection speed that can be passed to the core when PCS
244 is supported. For example, this is used in case of SGMII and
250 Creates and registers an MDIO bus.
254 const: snps,dwmac-mdio
267 snps,reset-active-low: ["snps,reset-gpio"]
268 snps,reset-delay-us: ["snps,reset-gpio"]
271 - $ref: "ethernet-controller.yaml#"
277 - allwinner,sun7i-a20-gmac
278 - allwinner,sun8i-a83t-emac
279 - allwinner,sun8i-h3-emac
280 - allwinner,sun8i-r40-emac
281 - allwinner,sun8i-v3s-emac
282 - allwinner,sun50i-a64-emac
291 - $ref: /schemas/types.yaml#definitions/uint32
294 Programmable Burst Length (tx and rx)
298 - $ref: /schemas/types.yaml#definitions/uint32
301 Tx Programmable Burst Length. If set, DMA tx will use this
302 value rather than snps,pbl.
306 - $ref: /schemas/types.yaml#definitions/uint32
309 Rx Programmable Burst Length. If set, DMA rx will use this
310 value rather than snps,pbl.
313 $ref: /schemas/types.yaml#definitions/flag
315 Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
316 rev < 3.50, don\'t multiply the values by 4.
323 - allwinner,sun7i-a20-gmac
324 - allwinner,sun8i-a83t-emac
325 - allwinner,sun8i-h3-emac
326 - allwinner,sun8i-r40-emac
327 - allwinner,sun8i-v3s-emac
328 - allwinner,sun50i-a64-emac
337 $ref: /schemas/types.yaml#definitions/flag
339 Enables the TSO feature otherwise it will be managed by
340 MAC HW capability register.
344 stmmac_axi_setup: stmmac-axi-config {
345 snps,wr_osr_lmt = <0xf>;
346 snps,rd_osr_lmt = <0xf>;
347 snps,blen = <256 128 64 32 0 0 0>;
350 mtl_rx_setup: rx-queues-config {
351 snps,rx-queues-to-use = <1>;
355 snps,map-to-dma-channel = <0x0>;
356 snps,priority = <0x0>;
360 mtl_tx_setup: tx-queues-config {
361 snps,tx-queues-to-use = <2>;
364 snps,weight = <0x10>;
366 snps,priority = <0x0>;
371 snps,send_slope = <0x1000>;
372 snps,idle_slope = <0x1000>;
373 snps,high_credit = <0x3E800>;
374 snps,low_credit = <0xFFC18000>;
375 snps,priority = <0x1>;
379 gmac0: ethernet@e0800000 {
380 compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
381 reg = <0xe0800000 0x8000>;
382 interrupt-parent = <&vic1>;
383 interrupts = <24 23 22>;
384 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
385 mac-address = [000000000000]; /* Filled in by U-Boot */
386 max-frame-size = <3800>;
388 snps,multicast-filter-bins = <256>;
389 snps,perfect-filter-entries = <128>;
390 rx-fifo-depth = <16384>;
391 tx-fifo-depth = <16384>;
393 clock-names = "stmmaceth";
394 snps,axi-config = <&stmmac_axi_setup>;
395 snps,mtl-rx-config = <&mtl_rx_setup>;
396 snps,mtl-tx-config = <&mtl_tx_setup>;
398 #address-cells = <1>;
400 compatible = "snps,dwmac-mdio";
401 phy1: ethernet-phy@0 {
407 # FIXME: We should set it, but it would report all the generic
408 # properties as additional properties.
409 # additionalProperties: false