1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/snps,dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare MAC
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
14 # Select every compatible, including the deprecated ones. This way, we
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
17 # as a valid value in the compatible property description
45 # We need to include all the compatibles from schemas that will
46 # include that schemas, otherwise compatible won't validate for
51 - allwinner,sun7i-a20-gmac
52 - allwinner,sun8i-a83t-emac
53 - allwinner,sun8i-h3-emac
54 - allwinner,sun8i-r40-gmac
55 - allwinner,sun8i-v3s-emac
56 - allwinner,sun50i-a64-emac
57 - amlogic,meson6-dwmac
58 - amlogic,meson8b-dwmac
59 - amlogic,meson8m2-dwmac
60 - amlogic,meson-gxbb-dwmac
61 - amlogic,meson-axg-dwmac
71 - qcom,sc8280xp-ethqos
73 - renesas,r9a06g032-gmac
76 - rockchip,rk3128-gmac
77 - rockchip,rk3228-gmac
78 - rockchip,rk3288-gmac
79 - rockchip,rk3328-gmac
80 - rockchip,rk3366-gmac
81 - rockchip,rk3368-gmac
82 - rockchip,rk3588-gmac
83 - rockchip,rk3399-gmac
84 - rockchip,rv1108-gmac
98 - starfive,jh7100-dwmac
99 - starfive,jh7110-dwmac
108 - description: Combined signal for various interrupt events
109 - description: The interrupt to manage the remote wake-up packet detection
110 - description: The interrupt that occurs when Rx exits the LPI state
111 - description: The interrupt that occurs when HW safety error triggered
117 - enum: [eth_wake_irq, eth_lpi, sfty]
118 - enum: [eth_wake_irq, eth_lpi, sfty]
119 - enum: [eth_wake_irq, eth_lpi, sfty]
124 additionalItems: true
126 - description: GMAC main clock
127 - description: Peripheral registers interface clock
129 PTP reference clock. This clock is used for programming the
130 Timestamp Addend Register. If not passed then the system
131 clock will be used and this is fine on some platforms.
136 additionalItems: true
146 - description: GMAC stmmaceth reset
147 - description: AHB reset
152 - enum: [stmmaceth, ahb]
161 $ref: ethernet-controller.yaml#/properties/phy-connection-type
163 The property is identical to 'phy-mode', and assumes that there is mode
164 converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter
165 can be passive (no SW requirement), and requires that the MAC operate
166 in a different mode than the PHY in order to function.
169 $ref: /schemas/types.yaml#/definitions/phandle
171 AXI BUS Mode parameters. Phandle to a node that can contain the
173 * snps,lpi_en, enable Low Power Interface
174 * snps,xit_frm, unlock on WoL
175 * snps,wr_osr_lmt, max write outstanding req. limit
176 * snps,rd_osr_lmt, max read outstanding req. limit
177 * snps,kbbe, do not cross 1KiB boundary.
178 * snps,blen, this is a vector of supported burst length.
179 * snps,fb, fixed-burst
180 * snps,mb, mixed-burst
181 * snps,rb, rebuild INCRx Burst
184 $ref: /schemas/types.yaml#/definitions/phandle
186 Multiple RX Queues parameters. Phandle to a node that
187 implements the 'rx-queues-config' object described in
193 snps,rx-queues-to-use:
194 $ref: /schemas/types.yaml#/definitions/uint32
195 description: number of RX queues to be used in the driver
198 description: Strict priority
201 description: Weighted Strict priority
208 snps,rx-sched-wsp: false
214 snps,rx-sched-sp: false
217 description: Each subnode represents a queue.
222 description: Queue to be enabled as DCB
225 description: Queue to be enabled as AVB
226 snps,map-to-dma-channel:
227 $ref: /schemas/types.yaml#/definitions/uint32
228 description: DMA channel id to map
231 description: AV Untagged Control packets
234 description: PTP Packets
237 description: DCB Control Packets
240 description: Untagged Packets
241 snps,route-multi-broad:
243 description: Multicast & Broadcast Packets
245 $ref: /schemas/types.yaml#/definitions/uint32
246 description: Bitmask of the tagged frames priorities assigned to the queue
253 snps,avb-algorithm: false
259 snps,dcb-algorithm: false
265 snps,route-ptp: false
266 snps,route-dcbcp: false
268 snps,route-multi-broad: false
274 snps,route-avcp: false
275 snps,route-dcbcp: false
277 snps,route-multi-broad: false
283 snps,route-avcp: false
284 snps,route-ptp: false
286 snps,route-multi-broad: false
292 snps,route-avcp: false
293 snps,route-ptp: false
294 snps,route-dcbcp: false
295 snps,route-multi-broad: false
298 - snps,route-multi-broad
301 snps,route-avcp: false
302 snps,route-ptp: false
303 snps,route-dcbcp: false
305 additionalProperties: false
306 additionalProperties: false
309 $ref: /schemas/types.yaml#/definitions/phandle
311 Multiple TX Queues parameters. Phandle to a node that
312 implements the 'tx-queues-config' object described in
318 snps,tx-queues-to-use:
319 $ref: /schemas/types.yaml#/definitions/uint32
320 description: number of TX queues to be used in the driver
323 description: Weighted Round Robin
326 description: Weighted Fair Queuing
329 description: Deficit Weighted Round Robin
332 description: Strict priority
339 snps,tx-sched-wfq: false
340 snps,tx-sched-dwrr: false
341 snps,tx-sched-sp: false
347 snps,tx-sched-wrr: false
348 snps,tx-sched-dwrr: false
349 snps,tx-sched-sp: false
355 snps,tx-sched-wrr: false
356 snps,tx-sched-wfq: false
357 snps,tx-sched-sp: false
363 snps,tx-sched-wrr: false
364 snps,tx-sched-wfq: false
365 snps,tx-sched-dwrr: false
368 description: Each subnode represents a queue.
372 $ref: /schemas/types.yaml#/definitions/uint32
373 description: TX queue weight (if using a DCB weight algorithm)
376 description: TX queue will be working in DCB
380 TX queue will be working in AVB.
381 Queue 0 is reserved for legacy traffic and so no AVB is
382 available in this queue.
384 $ref: /schemas/types.yaml#/definitions/uint32
385 description: enable Low Power Interface
387 $ref: /schemas/types.yaml#/definitions/uint32
388 description: unlock on WoL
390 $ref: /schemas/types.yaml#/definitions/uint32
391 description: max write outstanding req. limit
393 $ref: /schemas/types.yaml#/definitions/uint32
394 description: max read outstanding req. limit
396 $ref: /schemas/types.yaml#/definitions/uint32
398 Bitmask of the tagged frames priorities assigned to the queue.
399 When a PFC frame is received with priorities matching the bitmask,
400 the queue is blocked from transmitting for the pause time specified
403 snps,coe-unsupported:
405 description: TX checksum offload is unsupported by the TX queue.
413 snps,avb-algorithm: false
419 snps,dcb-algorithm: false
421 additionalProperties: false
422 additionalProperties: false
430 snps,reset-active-low:
432 $ref: /schemas/types.yaml#/definitions/flag
434 Indicates that the PHY Reset is active low
436 snps,reset-delays-us:
439 Triplet of delays. The 1st cell is reset pre-delay in micro
440 seconds. The 2nd cell is reset pulse in micro seconds. The 3rd
441 cell is reset post-delay in micro seconds.
446 $ref: /schemas/types.yaml#/definitions/flag
448 Use Address-Aligned Beats
451 $ref: /schemas/types.yaml#/definitions/flag
453 Program the DMA to use the fixed burst mode
456 $ref: /schemas/types.yaml#/definitions/flag
458 Program the DMA to use the mixed burst mode
460 snps,force_thresh_dma_mode:
461 $ref: /schemas/types.yaml#/definitions/flag
463 Force DMA to use the threshold mode for both tx and rx
465 snps,force_sf_dma_mode:
466 $ref: /schemas/types.yaml#/definitions/flag
468 Force DMA to use the Store and Forward mode for both tx and
469 rx. This flag is ignored if force_thresh_dma_mode is set.
471 snps,en-tx-lpi-clockgating:
472 $ref: /schemas/types.yaml#/definitions/flag
474 Enable gating of the MAC TX clock during TX low-power mode
476 snps,multicast-filter-bins:
477 $ref: /schemas/types.yaml#/definitions/uint32
479 Number of multicast filter hash bins supported by this device
482 snps,perfect-filter-entries:
483 $ref: /schemas/types.yaml#/definitions/uint32
485 Number of perfect filter entries supported by this device
489 $ref: /schemas/types.yaml#/definitions/uint32
491 Port selection speed that can be passed to the core when PCS
492 is supported. For example, this is used in case of SGMII and
496 $ref: /schemas/types.yaml#/definitions/uint32
498 Frequency division factor for MDC clock.
502 unevaluatedProperties: false
504 Creates and registers an MDIO bus.
508 const: snps,dwmac-mdio
515 unevaluatedProperties: false
517 AXI BUS Mode parameters.
521 $ref: /schemas/types.yaml#/definitions/flag
523 enable Low Power Interface
526 $ref: /schemas/types.yaml#/definitions/flag
531 $ref: /schemas/types.yaml#/definitions/uint32
533 max write outstanding req. limit
536 $ref: /schemas/types.yaml#/definitions/uint32
538 max read outstanding req. limit
541 $ref: /schemas/types.yaml#/definitions/uint32
543 do not cross 1KiB boundary.
546 $ref: /schemas/types.yaml#/definitions/uint32-array
548 this is a vector of supported burst length.
553 $ref: /schemas/types.yaml#/definitions/flag
558 $ref: /schemas/types.yaml#/definitions/flag
563 $ref: /schemas/types.yaml#/definitions/flag
575 snps,reset-active-low: ["snps,reset-gpio"]
576 snps,reset-delays-us: ["snps,reset-gpio"]
579 - $ref: ethernet-controller.yaml#
585 - allwinner,sun7i-a20-gmac
586 - allwinner,sun8i-a83t-emac
587 - allwinner,sun8i-h3-emac
588 - allwinner,sun8i-r40-gmac
589 - allwinner,sun8i-v3s-emac
590 - allwinner,sun50i-a64-emac
596 - qcom,sa8775p-ethqos
597 - qcom,sc8280xp-ethqos
610 Programmable Burst Length (tx and rx)
611 $ref: /schemas/types.yaml#/definitions/uint32
612 enum: [1, 2, 4, 8, 16, 32]
616 Tx Programmable Burst Length. If set, DMA tx will use this
617 value rather than snps,pbl.
618 $ref: /schemas/types.yaml#/definitions/uint32
619 enum: [1, 2, 4, 8, 16, 32]
623 Rx Programmable Burst Length. If set, DMA rx will use this
624 value rather than snps,pbl.
625 $ref: /schemas/types.yaml#/definitions/uint32
626 enum: [1, 2, 4, 8, 16, 32]
629 $ref: /schemas/types.yaml#/definitions/flag
631 Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core
632 rev < 3.50, don\'t multiply the values by 4.
639 - allwinner,sun7i-a20-gmac
640 - allwinner,sun8i-a83t-emac
641 - allwinner,sun8i-h3-emac
642 - allwinner,sun8i-r40-gmac
643 - allwinner,sun8i-v3s-emac
644 - allwinner,sun50i-a64-emac
645 - loongson,ls2k-dwmac
646 - loongson,ls7a-dwmac
653 - qcom,sa8775p-ethqos
654 - qcom,sc8280xp-ethqos
668 $ref: /schemas/types.yaml#/definitions/flag
670 Enables the TSO feature otherwise it will be managed by
671 MAC HW capability register.
673 additionalProperties: true
677 gmac0: ethernet@e0800000 {
678 compatible = "snps,dwxgmac-2.10", "snps,dwxgmac";
679 reg = <0xe0800000 0x8000>;
680 interrupt-parent = <&vic1>;
681 interrupts = <24 23 22>;
682 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
683 mac-address = [000000000000]; /* Filled in by U-Boot */
684 max-frame-size = <3800>;
686 snps,multicast-filter-bins = <256>;
687 snps,perfect-filter-entries = <128>;
688 rx-fifo-depth = <16384>;
689 tx-fifo-depth = <16384>;
691 clock-names = "stmmaceth";
692 snps,axi-config = <&stmmac_axi_setup>;
693 snps,mtl-rx-config = <&mtl_rx_setup>;
694 snps,mtl-tx-config = <&mtl_tx_setup>;
696 stmmac_axi_setup: stmmac-axi-config {
697 snps,wr_osr_lmt = <0xf>;
698 snps,rd_osr_lmt = <0xf>;
699 snps,blen = <256 128 64 32 0 0 0>;
702 mtl_rx_setup: rx-queues-config {
703 snps,rx-queues-to-use = <1>;
707 snps,map-to-dma-channel = <0x0>;
708 snps,priority = <0x0>;
712 mtl_tx_setup: tx-queues-config {
713 snps,tx-queues-to-use = <2>;
716 snps,weight = <0x10>;
718 snps,priority = <0x0>;
723 snps,send_slope = <0x1000>;
724 snps,idle_slope = <0x1000>;
725 snps,high_credit = <0x3E800>;
726 snps,low_credit = <0xFFC18000>;
727 snps,priority = <0x1>;
732 #address-cells = <1>;
734 compatible = "snps,dwmac-mdio";
735 phy1: ethernet-phy@0 {
741 # FIXME: We should set it, but it would report all the generic
742 # properties as additional properties.
743 # additionalProperties: false