1 * Renesas Electronics Ethernet AVB
3 This file provides information on what the device node for the Ethernet AVB
7 - compatible: Must contain one or more of the following:
8 - "renesas,etheravb-r8a7743" for the R8A7743 SoC.
9 - "renesas,etheravb-r8a7745" for the R8A7745 SoC.
10 - "renesas,etheravb-r8a77470" for the R8A77470 SoC.
11 - "renesas,etheravb-r8a7790" for the R8A7790 SoC.
12 - "renesas,etheravb-r8a7791" for the R8A7791 SoC.
13 - "renesas,etheravb-r8a7792" for the R8A7792 SoC.
14 - "renesas,etheravb-r8a7793" for the R8A7793 SoC.
15 - "renesas,etheravb-r8a7794" for the R8A7794 SoC.
16 - "renesas,etheravb-rcar-gen2" as a fallback for the above
17 R-Car Gen2 and RZ/G1 devices.
19 - "renesas,etheravb-r8a7795" for the R8A7795 SoC.
20 - "renesas,etheravb-r8a7796" for the R8A7796 SoC.
21 - "renesas,etheravb-r8a77970" for the R8A77970 SoC.
22 - "renesas,etheravb-r8a77980" for the R8A77980 SoC.
23 - "renesas,etheravb-r8a77995" for the R8A77995 SoC.
24 - "renesas,etheravb-rcar-gen3" as a fallback for the above
27 When compatible with the generic version, nodes must list the
28 SoC-specific version corresponding to the platform first followed by
31 - reg: Offset and length of (1) the register block and (2) the stream buffer.
32 The region for the register block is mandatory.
33 The region for the stream buffer is optional, as it is only present on
34 R-Car Gen2 and RZ/G1 SoCs, and on R-Car H3 (R8A7795), M3-W (R8A7796),
36 - interrupts: A list of interrupt-specifiers, one for each entry in
38 If interrupt-names is not present, an interrupt specifier
39 for a single muxed interrupt.
40 - phy-mode: see ethernet.txt file in the same directory.
41 - phy-handle: see ethernet.txt file in the same directory.
42 - #address-cells: number of address cells for the MDIO bus, must be equal to 1.
43 - #size-cells: number of size cells on the MDIO bus, must be equal to 0.
44 - clocks: clock phandle and specifier pair.
45 - pinctrl-0: phandle, referring to a default pin configuration node.
48 - interrupt-parent: the phandle for the interrupt controller that services
49 interrupts for this device.
50 - interrupt-names: A list of interrupt names.
51 For the R-Car Gen 3 SoCs this property is mandatory;
52 it should include one entry per channel, named "ch%u",
53 where %u is the channel number ranging from 0 to 24.
54 For other SoCs this property is optional; if present
55 it should contain "mux" for a single muxed interrupt.
56 - pinctrl-names: pin configuration state name ("default").
57 - renesas,no-ether-link: boolean, specify when a board does not provide a proper
59 - renesas,ether-link-active-low: boolean, specify when the AVB_LINK signal is
60 active-low instead of normal active-high.
65 compatible = "renesas,etheravb-r8a7795", "renesas,etheravb-rcar-gen3";
66 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
67 interrupt-parent = <&gic>;
68 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
93 interrupt-names = "ch0", "ch1", "ch2", "ch3",
94 "ch4", "ch5", "ch6", "ch7",
95 "ch8", "ch9", "ch10", "ch11",
96 "ch12", "ch13", "ch14", "ch15",
97 "ch16", "ch17", "ch18", "ch19",
98 "ch20", "ch21", "ch22", "ch23",
100 clocks = <&cpg CPG_MOD 812>;
101 power-domains = <&cpg>;
102 phy-mode = "rgmii-id";
103 phy-handle = <&phy0>;
105 pinctrl-0 = <ðer_pins>;
106 pinctrl-names = "default";
107 renesas,no-ether-link;
108 #address-cells = <1>;
111 phy0: ethernet-phy@0 {
125 interrupt-parent = <&gpio2>;
126 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;