1 * Amlogic Meson DWMAC Ethernet controller
3 The device inherits all the properties of the dwmac/stmmac devices
4 described in the file stmmac.txt in the current directory with the
7 Required properties on all platforms:
9 - compatible: Depending on the platform this should be one of:
10 - "amlogic,meson6-dwmac"
11 - "amlogic,meson8b-dwmac"
12 - "amlogic,meson8m2-dwmac"
13 - "amlogic,meson-gxbb-dwmac"
14 Additionally "snps,dwmac" and any applicable more
15 detailed version number described in net/stmmac.txt
18 - reg: The first register range should be the one of the DWMAC
19 controller. The second range is is for the Amlogic specific
20 configuration (for example the PRG_ETHERNET register range
23 Required properties on Meson8b, Meson8m2, GXBB and newer:
24 - clock-names: Should contain the following:
25 - "stmmaceth" - see stmmac.txt
26 - "clkin0" - first parent clock of the internal mux
27 - "clkin1" - second parent clock of the internal mux
29 Optional properties on Meson8b, Meson8m2, GXBB and newer:
30 - amlogic,tx-delay-ns: The internal RGMII TX clock delay (provided
31 by this driver) in nanoseconds. Allowed values
32 are: 0ns, 2ns, 4ns, 6ns.
33 When phy-mode is set to "rgmii" then the TX
34 delay should be explicitly configured. When
35 not configured a fallback of 2ns is used.
36 When the phy-mode is set to either "rgmii-id"
37 or "rgmii-txid" the TX clock delay is already
38 provided by the PHY. In that case this
39 property should be set to 0ns (which disables
40 the TX clock delay in the MAC to prevent the
41 clock from going off because both PHY and MAC
43 Any configuration is ignored when the phy-mode
48 ethmac: ethernet@c9410000 {
49 compatible = "amlogic,meson6-dwmac", "snps,dwmac";
50 reg = <0xc9410000 0x10000
53 interrupt-names = "macirq";
55 clock-names = "stmmaceth";
59 ethmac: ethernet@c9410000 {
60 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
61 reg = <0x0 0xc9410000 0x0 0x10000>,
62 <0x0 0xc8834540 0x0 0x8>;
64 interrupt-names = "macirq";
65 clocks = <&clkc CLKID_ETH>,
66 <&clkc CLKID_FCLK_DIV2>,
68 clock-names = "stmmaceth", "clkin0", "clkin1";