1 * Faraday Technology FTGMAC100 gigabit ethernet controller
4 - compatible: "faraday,ftgmac100"
6 Must also contain one of these if used as part of an Aspeed AST2400
7 or 2500 family SoC as they have some subtle tweaks to the
10 - "aspeed,ast2400-mac"
11 - "aspeed,ast2500-mac"
12 - "aspeed,ast2600-mac"
14 - reg: Address and length of the register set for the device
15 - interrupts: Should contain ethernet controller interrupt
18 - phy-handle: See ethernet.txt file in the same directory.
19 - phy-mode: See ethernet.txt file in the same directory. If the property is
20 absent, "rgmii" is assumed. Supported values are "rgmii*" and "rmii" for
21 aspeed parts. Other (unknown) parts will accept any value.
22 - use-ncsi: Use the NC-SI stack instead of an MDIO PHY. Currently assumes
23 rmii (100bT) but kept as a separate property in case NC-SI grows support
25 - no-hw-checksum: Used to disable HW checksum support. Here for backward
26 compatibility as the driver now should have correct defaults based on
28 - clocks: In accordance with the generic clock bindings. Must describe the MAC
29 IP clock, and optionally an RMII RCLK gate for the AST2500/AST2600. The
30 required MAC clock must be the first cell.
33 - "MACCLK": The MAC IP clock
34 - "RCLK": Clock gate for the RMII RCLK
37 - mdio: See mdio.txt file in the same directory.
41 mac0: ethernet@1e660000 {
42 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
43 reg = <0x1e660000 0x180>;
48 Example with phy-handle:
50 mac1: ethernet@1e680000 {
51 compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
52 reg = <0x1e680000 0x180>;
63 compatible = "ethernet-phy-ieee802.3-c22";