1 =============================================================================
2 Freescale Frame Manager Device Bindings
8 - FMan dTSEC/XGEC/mEMAC Node
13 =============================================================================
18 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 etc.) the FMan node will have child nodes for each of them.
25 Value type: <stringlist>
26 Definition: Must include "fsl,fman"
27 FMan version can be determined via FM_IP_REV_1 register in the
28 FMan block. The offset is 0xc4 from the beginning of the
29 Frame Processing Manager memory map (0xc3000 from the
30 beginning of the FMan node).
35 Definition: Specifies the index of the FMan unit.
37 The cell-index value may be used by the SoC, to identify the
38 FMan unit in the SoC memory map. In the table below,
39 there's a description of the cell-index use in each SoC:
42 register[bit] FMan unit cell-index
43 ============================================================
46 - P2041, P3041, P4080 P5020, P5040:
47 register[bit] FMan unit cell-index
48 ============================================================
51 (Second FM available only in P4080 and P5040)
53 - B4860, T1040, T2080, T4240:
54 register[bit] FMan unit cell-index
55 ============================================================
56 DCFG_CCSR_DEVDISR2[24] 1 0
57 DCFG_CCSR_DEVDISR2[25] 2 1
58 (Second FM available only in T4240)
60 DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
61 the specific SoC "Device Configuration/Pin Control" Memory
66 Value type: <prop-encoded-array>
67 Definition: A standard property. Specifies the offset of the
68 following configuration registers:
69 - BMI configuration registers.
70 - QMI configuration registers.
71 - DMA configuration registers.
72 - FPM configuration registers.
73 - FMan controller configuration registers.
77 Value type: <prop-encoded-array>
78 Definition: A standard property.
82 Value type: <prop-encoded-array>
83 Definition: phandle for the fman input clock.
87 Value type: <stringlist>
88 Definition: "fmanclk" for the fman input clock.
92 Value type: <prop-encoded-array>
93 Definition: A pair of IRQs are specified in this property.
94 The first element is associated with the event interrupts and
95 the second element is associated with the error interrupts.
97 - fsl,qman-channel-range
99 Value type: <prop-encoded-array>
100 Definition: Specifies the range of the available dedicated
101 channels in the FMan. The first cell specifies the beginning
102 of the range and the second cell specifies the number of
104 Further information available at:
105 "Work Queue (WQ) Channel Assignments in the QMan" section
106 in DPAA Reference Manual.
111 Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
113 =============================================================================
118 FMan Internal memory - shared between all the FMan modules.
119 It contains data structures that are common and written to or read by
121 FMan internal memory is split into the following parts:
122 Packet buffering (Tx/Rx FIFOs)
123 Frames internal context
129 Value type: <stringlist>
130 Definition: Must include "fsl,fman-muram"
134 Value type: <prop-encoded-array>
135 Definition: A standard property.
136 Specifies the multi-user memory offset and the size within
142 compatible = "fsl,fman-muram";
143 ranges = <0 0x000000 0x28000>;
146 =============================================================================
151 The Frame Manager (FMan) supports several types of hardware ports:
152 Ethernet receiver (RX)
153 Ethernet transmitter (TX)
154 Offline/Host command (O/H)
160 Value type: <stringlist>
161 Definition: A standard property.
162 Must include one of the following:
163 - "fsl,fman-v2-port-oh" for FManV2 OH ports
164 - "fsl,fman-v2-port-rx" for FManV2 RX ports
165 - "fsl,fman-v2-port-tx" for FManV2 TX ports
166 - "fsl,fman-v3-port-oh" for FManV3 OH ports
167 - "fsl,fman-v3-port-rx" for FManV3 RX ports
168 - "fsl,fman-v3-port-tx" for FManV3 TX ports
173 Definition: Specifies the hardware port id.
174 Each hardware port on the FMan has its own hardware PortID.
175 Super set of all hardware Port IDs available at FMan Reference
176 Manual under "FMan Hardware Ports in Freescale Devices" table.
178 Each hardware port is assigned a 4KB, port-specific page in
179 the FMan hardware port memory region (which is part of the
180 FMan memory map). The first 4 KB in the FMan hardware ports
181 memory region is used for what are called common registers.
182 The subsequent 63 4KB pages are allocated to the hardware
184 The page of a specific port is determined by the cell-index.
188 Value type: <prop-encoded-array>
189 Definition: There is one reg region describing the port
190 configuration registers.
195 Definition: The default port rate is 1G.
196 If this property exists, the port is s 10G port.
198 - fsl,fman-best-effort-port
201 Definition: Can be defined only if 10G-support is set.
202 This property marks a best-effort 10G port (10G port that
203 may not be capable of line rate).
209 compatible = "fsl,fman-v2-port-tx";
210 reg = <0xa8000 0x1000>;
215 compatible = "fsl,fman-v2-port-rx";
216 reg = <0x88000 0x1000>;
221 compatible = "fsl,fman-v2-port-oh";
222 reg = <0x81000 0x1000>;
225 =============================================================================
226 FMan dTSEC/XGEC/mEMAC Node
230 mEMAC/dTSEC/XGEC are the Ethernet network interfaces
236 Value type: <stringlist>
237 Definition: A standard property.
238 Must include one of the following:
239 - "fsl,fman-dtsec" for dTSEC MAC
240 - "fsl,fman-xgec" for XGEC MAC
241 - "fsl,fman-memac" for mEMAC MAC
246 Definition: Specifies the MAC id.
248 The cell-index value may be used by the FMan or the SoC, to
249 identify the MAC unit in the FMan (or SoC) memory map.
250 In the tables below there's a description of the cell-index
251 use, there are two tables, one describes the use of cell-index
252 by the FMan, the second describes the use by the SoC:
257 register[bit] MAC cell-index
258 ============================================================
260 FM_EPI[16+n] dTSECn n-1
261 FM_NPI[11+n] dTSECn n-1
265 register[bit] MAC cell-index
266 ============================================================
267 FM_EPI[16+n] mEMACn n-1
270 FM_NPI[11+n] mEMACn n-1
275 FM_EPI and FM_NPI are located in the FMan memory map.
279 - P2041, P3041, P4080 P5020, P5040:
280 register[bit] FMan MAC cell
282 ============================================================
283 DCFG_DEVDISR2[7] 1 XGEC 8
284 DCFG_DEVDISR2[7+n] 1 dTSECn n-1
285 DCFG_DEVDISR2[15] 2 XGEC 8
286 DCFG_DEVDISR2[15+n] 2 dTSECn n-1
289 - T1040, T2080, T4240, B4860:
290 register[bit] FMan MAC cell
292 ============================================================
293 DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
294 DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
297 EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
298 the specific SoC "Device Configuration/Pin Control" Memory
303 Value type: <prop-encoded-array>
304 Definition: A standard property.
308 Value type: <prop-encoded-array>
309 Definition: An array of two phandles - the first references is
310 the FMan RX port and the second is the TX port used by this
315 Value type: <phandle>
316 Definition: A phandle for 1EEE1588 timer.
319 Usage required for "fsl,fman-memac" MACs
320 Value type: <phandle>
321 Definition: A phandle for pcsphy.
324 Usage required for "fsl,fman-dtsec" MACs
325 Value type: <phandle>
326 Definition: A phandle for tbiphy.
330 fman1_tx28: port@a8000 {
332 compatible = "fsl,fman-v2-port-tx";
333 reg = <0xa8000 0x1000>;
336 fman1_rx8: port@88000 {
338 compatible = "fsl,fman-v2-port-rx";
339 reg = <0x88000 0x1000>;
342 ptp-timer: ptp_timer@fe000 {
343 compatible = "fsl,fman-ptp-timer";
344 reg = <0xfe000 0x1000>;
348 compatible = "fsl,fman-dtsec";
350 reg = <0xe0000 0x1000>;
351 fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
352 ptp-timer = <&ptp-timer>;
353 tbi-handle = <&tbi0>;
356 ============================================================================
359 Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
361 =============================================================================
366 The MDIO is a bus to which the PHY devices are connected.
372 Value type: <stringlist>
373 Definition: A standard property.
374 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
375 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
376 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
381 Value type: <prop-encoded-array>
382 Definition: A standard property.
387 Definition: Specifies the external MDIO bus clock speed to
388 be used, if different from the standard 2.5 MHz.
389 This may be due to the standard speed being unsupported (e.g.
390 due to a hardware problem), or to advertise that all relevant
391 components in the system support a faster speed.
394 Usage: required for external MDIO
395 Value type: <prop-encoded-array>
396 Definition: Event interrupt of external MDIO controller.
398 - fsl,fman-internal-mdio
399 Usage: required for internal MDIO
401 Definition: Fman has internal MDIO for internal PCS(Physical
402 Coding Sublayer) PHYs and external MDIO for external PHYs.
403 The settings and programming routines for internal/external
404 MDIO are different. Must be included for internal MDIO.
406 For internal PHY device on internal mdio bus, a PHY node should be created.
407 See the definition of the PHY node in booting-without-of.txt for an
408 example of how to define a PHY (Internal PHY has no interrupt line).
409 - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
410 - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
411 PCS PHY addr must be '0'.
415 Example for FMan v2 external MDIO:
418 compatible = "fsl,fman-xmdio";
419 reg = <0xf1000 0x1000>;
420 interrupts = <101 2 0 0>;
423 Example for FMan v2 internal MDIO:
426 compatible = "fsl,fman-mdio";
427 reg = <0xe3120 0xee0>;
428 fsl,fman-internal-mdio;
432 device_type = "tbi-phy";
436 Example for FMan v3 internal MDIO:
439 compatible = "fsl,fman-memac-mdio";
440 reg = <0xf1000 0x1000>;
441 fsl,fman-internal-mdio;
443 pcsphy6: ethernet-phy@0 {
448 =============================================================================
452 #address-cells = <1>;
455 compatible = "fsl,fman"
456 ranges = <0 0x400000 0x100000>;
457 reg = <0x400000 0x100000>;
458 clocks = <&fman_clk>;
459 clock-names = "fmanclk";
463 fsl,qman-channel-range = <0x40 0xc>;
466 compatible = "fsl,fman-muram";
472 compatible = "fsl,fman-v2-port-oh";
473 reg = <0x81000 0x1000>;
478 compatible = "fsl,fman-v2-port-oh";
479 reg = <0x82000 0x1000>;
484 compatible = "fsl,fman-v2-port-oh";
485 reg = <0x83000 0x1000>;
490 compatible = "fsl,fman-v2-port-oh";
491 reg = <0x84000 0x1000>;
496 compatible = "fsl,fman-v2-port-oh";
497 reg = <0x85000 0x1000>;
502 compatible = "fsl,fman-v2-port-oh";
503 reg = <0x86000 0x1000>;
506 fman1_rx_0x8: port@88000 {
508 compatible = "fsl,fman-v2-port-rx";
509 reg = <0x88000 0x1000>;
512 fman1_rx_0x9: port@89000 {
514 compatible = "fsl,fman-v2-port-rx";
515 reg = <0x89000 0x1000>;
518 fman1_rx_0xa: port@8a000 {
520 compatible = "fsl,fman-v2-port-rx";
521 reg = <0x8a000 0x1000>;
524 fman1_rx_0xb: port@8b000 {
526 compatible = "fsl,fman-v2-port-rx";
527 reg = <0x8b000 0x1000>;
530 fman1_rx_0xc: port@8c000 {
532 compatible = "fsl,fman-v2-port-rx";
533 reg = <0x8c000 0x1000>;
536 fman1_rx_0x10: port@90000 {
538 compatible = "fsl,fman-v2-port-rx";
539 reg = <0x90000 0x1000>;
542 fman1_tx_0x28: port@a8000 {
544 compatible = "fsl,fman-v2-port-tx";
545 reg = <0xa8000 0x1000>;
548 fman1_tx_0x29: port@a9000 {
550 compatible = "fsl,fman-v2-port-tx";
551 reg = <0xa9000 0x1000>;
554 fman1_tx_0x2a: port@aa000 {
556 compatible = "fsl,fman-v2-port-tx";
557 reg = <0xaa000 0x1000>;
560 fman1_tx_0x2b: port@ab000 {
562 compatible = "fsl,fman-v2-port-tx";
563 reg = <0xab000 0x1000>;
566 fman1_tx_0x2c: port@ac0000 {
568 compatible = "fsl,fman-v2-port-tx";
569 reg = <0xac000 0x1000>;
572 fman1_tx_0x30: port@b0000 {
574 compatible = "fsl,fman-v2-port-tx";
575 reg = <0xb0000 0x1000>;
579 compatible = "fsl,fman-dtsec";
581 reg = <0xe0000 0x1000>;
582 fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
583 tbi-handle = <&tbi5>;
587 compatible = "fsl,fman-dtsec";
589 reg = <0xe2000 0x1000>;
590 fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
591 tbi-handle = <&tbi6>;
595 compatible = "fsl,fman-dtsec";
597 reg = <0xe4000 0x1000>;
598 fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
599 tbi-handle = <&tbi7>;
603 compatible = "fsl,fman-dtsec";
605 reg = <0xe6000 0x1000>;
606 fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
607 tbi-handle = <&tbi8>;
611 compatible = "fsl,fman-dtsec";
613 reg = <0xf0000 0x1000>;
614 fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
615 tbi-handle = <&tbi9>;
619 compatible = "fsl,fman-xgec";
620 reg = <0xf0000 0x1000>;
621 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
625 compatible = "fsl,fman-ptp-timer";
626 reg = <0xfe000 0x1000>;
630 compatible = "fsl,fman-xmdio";
631 reg = <0xf1000 0x1000>;
632 interrupts = <101 2 0 0>;