1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/fsl,fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Fast Ethernet Controller (FEC)
10 - Joakim Zhang <qiangqing.zhang@nxp.com>
13 - $ref: ethernet-controller.yaml#
28 - const: fsl,imx25-fec
33 - const: fsl,imx27-fec
38 - const: fsl,imx6q-fec
42 - const: fsl,imx6sx-fec
44 - const: fsl,imx8mq-fec
45 - const: fsl,imx6sx-fec
51 - const: fsl,imx8mq-fec
52 - const: fsl,imx6sx-fec
54 - const: fsl,imx8qm-fec
55 - const: fsl,imx6sx-fec
59 - const: fsl,imx8qm-fec
60 - const: fsl,imx6sx-fec
90 The "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing.
91 The "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock.
92 The "ptp"(option), for IEEE1588 timer clock that requires the clock.
93 The "enet_clk_ref"(option), for MAC transmit/receiver reference clock like
94 RGMII TXC clock or RMII reference clock. It depends on board design,
95 the clock is required if RGMII TXC and RMII reference clock source from
97 The "enet_out"(option), output clock for external device, like supply clock
98 for PHY. The clock is required if PHY clock source from SOC.
99 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
100 The clock is required if SoC RGMII enable clock delay.
120 local-mac-address: true
124 tx-internal-delay-ps:
127 rx-internal-delay-ps:
132 Regulator that powers the Ethernet PHY.
135 $ref: /schemas/types.yaml#/definitions/uint32
137 The property is valid for enet-avb IP, which supports hw multi queues.
138 Should specify the tx queue number, otherwise set tx queue number to 1.
142 $ref: /schemas/types.yaml#/definitions/uint32
144 The property is valid for enet-avb IP, which supports hw multi queues.
145 Should specify the rx queue number, otherwise set rx queue number to 1.
149 $ref: /schemas/types.yaml#/definitions/flag
151 If present, indicates that the hardware supports waking up via magic packet.
153 fsl,err006687-workaround-present:
154 $ref: /schemas/types.yaml#/definitions/flag
156 If present indicates that the system has the hardware workaround for
157 ERR006687 applied and does not need a software workaround.
160 $ref: /schemas/types.yaml#/definitions/phandle-array
162 Register bits of stop mode control, the format is <&gpr req_gpr req_bit>.
163 gpr is the phandle to general purpose register node.
164 req_gpr is the gpr register offset for ENET stop request.
165 req_bit is the gpr bit offset for ENET stop request.
170 Specifies the mdio bus in the FEC, used as a container for phy nodes.
172 # Deprecated optional properties:
173 # To avoid these, create a phy node according to ethernet-phy.yaml in the same
174 # directory, and point the FEC's "phy-handle" property to it. Then use
175 # the phy's reset binding, again described by ethernet-phy.yaml.
180 Should specify the gpio for phy reset.
185 Reset duration in milliseconds. Should present only if property
186 "phy-reset-gpios" is available. Missing the property will have the
187 duration be 1 millisecond. Numbers greater than 1000 are invalid
188 and 1 millisecond will be used instead.
190 phy-reset-active-high:
193 If present then the reset sequence using the GPIO specified in the
194 "phy-reset-gpios" property is reversed (H=reset state, L=operation state).
196 phy-reset-post-delay:
199 Post reset delay in milliseconds. If present then a delay of phy-reset-post-delay
200 milliseconds will be observed after the phy-reset-gpios has been toggled.
201 Can be omitted thus no delay is observed. Delay is in range of 1ms to 1000ms.
202 Other delays are invalid.
209 # FIXME: We had better set additionalProperties to false to avoid invalid or at
210 # least undocumented properties. However, PHY may have a deprecated option to
211 # place PHY OF properties in the MAC node, such as Micrel PHY, and we can find
212 # these boards which is based on i.MX6QDL.
213 additionalProperties: false
218 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
219 reg = <0x83fec000 0x4000>;
222 phy-reset-gpios = <&gpio2 14 0>;
223 phy-supply = <®_fec_supply>;
227 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
228 reg = <0x83fed000 0x4000>;
231 phy-reset-gpios = <&gpio2 14 0>;
232 phy-supply = <®_fec_supply>;
233 phy-handle = <ðphy0>;
236 #address-cells = <1>;
239 ethphy0: ethernet-phy@0 {
240 compatible = "ethernet-phy-ieee802.3-c22";