1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet Controller Generic Binding
10 - David S. Miller <davem@davemloft.net>
14 pattern: "^ethernet(@.*)?$"
18 Specifies the MAC address that was assigned to the network device.
19 $ref: /schemas/types.yaml#/definitions/uint8-array
26 Specifies the MAC address that was last used by the boot
27 program; should be used in cases where the MAC address assigned
28 to the device by the boot program is different from the
29 local-mac-address property.
30 $ref: /schemas/types.yaml#/definitions/uint8-array
36 $ref: /schemas/types.yaml#/definitions/uint32
38 Maximum transfer unit (IEEE defined MTU), rather than the
39 maximum frame size (there\'s contradiction in the Devicetree
43 $ref: /schemas/types.yaml#/definitions/uint32
45 Specifies maximum speed in Mbit/s supported by the device.
50 Reference to an nvmem node for the MAC address
57 Specifies interface type between the Ethernet device and a physical
60 # There is not a standard bus between the MAC and the PHY,
61 # something proprietary is being used to embed the PHY in the
73 # RX and TX delays are added by the MAC when required
76 # RGMII with internal RX and TX delays provided by the PHY,
77 # the MAC should not add the RX or TX delays in this case
80 # RGMII with internal RX delay provided by the PHY, the MAC
81 # should not add an RX delay in this case
84 # RGMII with internal TX delay provided by the PHY, the MAC
85 # should not add an TX delay in this case
97 # 10GBASE-KR, XFI, SFI
104 $ref: "#/properties/phy-connection-type"
107 $ref: /schemas/types.yaml#/definitions/phandle
109 Specifies a reference to a node representing a PHY device.
112 $ref: "#/properties/phy-handle"
116 $ref: "#/properties/phy-handle"
120 $ref: /schemas/types.yaml#/definitions/uint32
122 The size of the controller\'s receive fifo in bytes. This is used
123 for components that can have configurable receive fifo sizes,
124 and is useful for determining certain configuration settings
125 such as flow control thresholds.
127 rx-internal-delay-ps:
129 RGMII Receive Clock Delay defined in pico seconds.
130 This is used for controllers that have configurable RX internal delays.
131 If this property is present then the MAC applies the RX delay.
134 $ref: /schemas/types.yaml#/definitions/phandle
136 Specifies a reference to a node representing a SFP cage.
139 $ref: /schemas/types.yaml#/definitions/uint32
141 The size of the controller\'s transmit fifo in bytes. This
142 is used for components that can have configurable fifo sizes.
144 tx-internal-delay-ps:
146 RGMII Transmit Clock Delay defined in pico seconds.
147 This is used for controllers that have configurable TX internal delays.
148 If this property is present then the MAC applies the TX delay.
152 Specifies the PHY management type. If auto is set and fixed-link
153 is not specified, it uses MDIO for management.
154 $ref: /schemas/types.yaml#/definitions/string
173 Emulated PHY ID, choose any but unique to the all
174 specified fixed-links
178 Duplex configuration. 0 for half duplex or 1 for
181 - enum: [10, 100, 1000]
183 Link speed in Mbits/sec.
187 Pause configuration. 0 for no pause, 1 for pause
191 Asymmetric pause configuration. 0 for no asymmetric
192 pause, 1 for asymmetric pause
202 $ref: /schemas/types.yaml#/definitions/uint32
203 enum: [10, 100, 1000]
206 $ref: /schemas/types.yaml#/definitions/flag
208 Indicates that full-duplex is used. When absent, half
212 $ref: /schemas/types.yaml#definitions/flag
214 Indicates that pause should be enabled.
217 $ref: /schemas/types.yaml#/definitions/flag
219 Indicates that asym_pause should be enabled.
224 GPIO to determine if the link is up
229 additionalProperties: true