1 * Qualcomm Atheros QCA8xxx switch family
5 - compatible: should be one of:
9 - #size-cells: must be 0
10 - #address-cells: must be 1
14 The integrated switch subnode should be specified according to the binding
15 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
16 mdio-bus each subnode describing a port needs to have a valid phandle
17 referencing the internal PHY it is connected to. This is because there's no
18 N:N mapping of port and PHY id.
20 Don't use mixed external and internal mdio-bus configurations, as this is
21 not supported by the hardware.
23 The CPU port of this switch is always port 0.
25 A CPU port node has the following optional node:
27 - fixed-link : Fixed-link subnode describing a link to a non-MDIO
29 Documentation/devicetree/bindings/net/fixed-link.txt
32 For QCA8K the 'fixed-link' sub-node supports only the following properties:
34 - 'speed' (integer, mandatory), to indicate the link speed. Accepted
35 values are 10, 100 and 1000
36 - 'full-duplex' (boolean, optional), to indicate that full duplex is
37 used. When absent, half duplex is assumed.
41 for the external mdio-bus configuration:
65 compatible = "qca,qca8337";
88 phy-handle = <&phy_port1>;
94 phy-handle = <&phy_port2>;
100 phy-handle = <&phy_port3>;
106 phy-handle = <&phy_port4>;
112 phy-handle = <&phy_port5>;
118 for the internal master mdio-bus configuration:
122 compatible = "qca,qca8337";
123 #address-cells = <1>;
129 #address-cells = <1>;