Documentation/devicetree/bindings/net/dsa/qca8k.txt

   1 * Qualcomm Atheros QCA8xxx switch family
   2
   3 Required properties:
   4
   5 - compatible: should be one of:
   6     "qca,qca8334"
   7     "qca,qca8337"
   8
   9 - #size-cells: must be 0
  10 - #address-cells: must be 1
  11
  12 Subnodes:
  13
  14 The integrated switch subnode should be specified according to the binding
  15 described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
  16 mdio-bus each subnode describing a port needs to have a valid phandle
  17 referencing the internal PHY it is connected to. This is because there's no
  18 N:N mapping of port and PHY id.
  19
  20 Don't use mixed external and internal mdio-bus configurations, as this is
  21 not supported by the hardware.
  22
  23 The CPU port of this switch is always port 0.
  24
  25 A CPU port node has the following optional node:
  26
  27 - fixed-link            : Fixed-link subnode describing a link to a non-MDIO
  28                           managed entity. See
  29                           Documentation/devicetree/bindings/net/fixed-link.txt
  30                           for details.
  31
  32 For QCA8K the 'fixed-link' sub-node supports only the following properties:
  33
  34 - 'speed' (integer, mandatory), to indicate the link speed. Accepted
  35   values are 10, 100 and 1000
  36 - 'full-duplex' (boolean, optional), to indicate that full duplex is
  37   used. When absent, half duplex is assumed.
  38
  39 Examples:
  40
  41 for the external mdio-bus configuration:
  42
  43         &mdio0 {
  44                 phy_port1: phy@0 {
  45                         reg = <0>;
  46                 };
  47
  48                 phy_port2: phy@1 {
  49                         reg = <1>;
  50                 };
  51
  52                 phy_port3: phy@2 {
  53                         reg = <2>;
  54                 };
  55
  56                 phy_port4: phy@3 {
  57                         reg = <3>;
  58                 };
  59
  60                 phy_port5: phy@4 {
  61                         reg = <4>;
  62                 };
  63
  64                 switch@10 {
  65                         compatible = "qca,qca8337";
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68
  69                         reg = <0x10>;
  70
  71                         ports {
  72                                 #address-cells = <1>;
  73                                 #size-cells = <0>;
  74                                 port@0 {
  75                                         reg = <0>;
  76                                         label = "cpu";
  77                                         ethernet = <&gmac1>;
  78                                         phy-mode = "rgmii";
  79                                         fixed-link {
  80                                                 speed = 1000;
  81                                                 full-duplex;
  82                                         };
  83                                 };
  84
  85                                 port@1 {
  86                                         reg = <1>;
  87                                         label = "lan1";
  88                                         phy-handle = <&phy_port1>;
  89                                 };
  90
  91                                 port@2 {
  92                                         reg = <2>;
  93                                         label = "lan2";
  94                                         phy-handle = <&phy_port2>;
  95                                 };
  96
  97                                 port@3 {
  98                                         reg = <3>;
  99                                         label = "lan3";
 100                                         phy-handle = <&phy_port3>;
 101                                 };
 102
 103                                 port@4 {
 104                                         reg = <4>;
 105                                         label = "lan4";
 106                                         phy-handle = <&phy_port4>;
 107                                 };
 108
 109                                 port@5 {
 110                                         reg = <5>;
 111                                         label = "wan";
 112                                         phy-handle = <&phy_port5>;
 113                                 };
 114                         };
 115                 };
 116         };
 117
 118 for the internal master mdio-bus configuration:
 119
 120         &mdio0 {
 121                 switch@10 {
 122                         compatible = "qca,qca8337";
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125
 126                         reg = <0x10>;
 127
 128                         ports {
 129                                 #address-cells = <1>;
 130                                 #size-cells = <0>;
 131
 132                                 port@0 {
 133                                         reg = <0>;
 134                                         label = "cpu";
 135                                         ethernet = <&gmac1>;
 136                                         phy-mode = "rgmii";
 137                                         fixed-link {
 138                                                 speed = 1000;
 139                                                 full-duplex;
 140                                         };
 141                                 };
 142
 143                                 port@1 {
 144                                         reg = <1>;
 145                                         label = "lan1";
 146                                 };
 147
 148                                 port@2 {
 149                                         reg = <2>;
 150                                         label = "lan2";
 151                                 };
 152
 153                                 port@3 {
 154                                         reg = <3>;
 155                                         label = "lan3";
 156                                 };
 157
 158                                 port@4 {
 159                                         reg = <4>;
 160                                         label = "lan4";
 161                                 };
 162
 163                                 port@5 {
 164                                         reg = <5>;
 165                                         label = "wan";
 166                                 };
 167                         };
 168                 };
 169         };