1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019 BayLibre, SAS
5 $id: "http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic Meson DWMAC Ethernet controller
11 - Neil Armstrong <narmstrong@baylibre.com>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
14 # We need a select here so we don't match all nodes with 'snps,dwmac'
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
24 - amlogic,meson-axg-dwmac
29 - $ref: "snps,dwmac.yaml#"
35 - amlogic,meson8b-dwmac
36 - amlogic,meson8m2-dwmac
37 - amlogic,meson-gxbb-dwmac
38 - amlogic,meson-axg-dwmac
46 - description: GMAC main clock
47 - description: First parent clock of the internal mux
48 - description: Second parent clock of the internal mux
49 - description: The clock which drives the timing adjustment logic
58 - const: timing-adjustment
61 $ref: /schemas/types.yaml#definitions/uint32
63 The internal RGMII TX clock delay (provided by this driver) in
64 nanoseconds. Allowed values are 0ns, 2ns, 4ns, 6ns.
65 When phy-mode is set to "rgmii" then the TX delay should be
66 explicitly configured. When not configured a fallback of 2ns is
67 used. When the phy-mode is set to either "rgmii-id" or "rgmii-txid"
68 the TX clock delay is already provided by the PHY. In that case
69 this property should be set to 0ns (which disables the TX clock
70 delay in the MAC to prevent the clock from going off because both
71 PHY and MAC are adding a delay).
72 Any configuration is ignored when the phy-mode is set to "rmii".
80 The internal RGMII RX clock delay (provided by this IP block) in
81 nanoseconds. When phy-mode is set to "rgmii" then the RX delay
82 should be explicitly configured. When the phy-mode is set to
83 either "rgmii-id" or "rgmii-rxid" the RX clock delay is already
84 provided by the PHY. Any configuration is ignored when the
85 phy-mode is set to "rmii".
93 - amlogic,meson6-dwmac
94 - amlogic,meson8b-dwmac
95 - amlogic,meson8m2-dwmac
96 - amlogic,meson-gxbb-dwmac
97 - amlogic,meson-axg-dwmac
106 The first register range should be the one of the DWMAC controller
108 The second range is is for the Amlogic specific configuration
109 (for example the PRG_ETHERNET register range on Meson8b and newer)
122 ethmac: ethernet@c9410000 {
123 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
124 reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
126 interrupt-names = "macirq";
127 clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
128 clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";