1 # SPDX-License-Identifier: GPL-2.0+
4 $id: http://devicetree.org/schemas/net/adi,adin.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Alexandru Ardelean <alexandru.ardelean@analog.com>
13 Bindings for Analog Devices Industrial Ethernet PHYs
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
23 enum: [ 1600, 1800, 2000, 2200, 2400 ]
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
29 internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
30 enum: [ 1600, 1800, 2000, 2200, 2400 ]
35 When operating in RMII mode, this option configures the FIFO depth.
36 enum: [ 4, 8, 12, 16, 20, 24 ]
39 unevaluatedProperties: false
47 phy-mode = "rgmii-id";
52 adi,rx-internal-delay-ps = <1800>;
53 adi,tx-internal-delay-ps = <2200>;
66 adi,fifo-depth-bits = <16>;