1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware Mobile Storage Host Controller
10 - Ulf Hansson <ulf.hansson@linaro.org>
12 # Everything else is described in the common file
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
30 Handle to "biu" and "ciu" clocks for the
31 bus interface unit clock and the card interface unit clock.
42 $ref: /schemas/types.yaml#/definitions/phandle-array
45 - description: phandle to the sysmgr node
46 - description: register offset that controls the SDMMC clock phase
47 - description: register shift for the smplsel(drive in) setting
49 This property is optional. Contains the phandle to System Manager block
50 that contains the SDMMC clock-phase control register. The first value is
51 the pointer to the sysmgr, the 2nd value is the register offset for the
52 SDMMC clock phase register, and the 3rd value is the bit shift for the
53 smplsel(drive in) setting.
56 - $ref: synopsys-dw-mshc-common.yaml#
62 const: altr,socfpga-dw-mshc
65 altr,sysmgr-syscon: true
69 altr,sysmgr-syscon: false
78 unevaluatedProperties: false
83 compatible = "snps,dw-mshc";
84 reg = <0x12200000 0x1000>;
85 interrupts = <0 75 0>;
86 clocks = <&clock 351>, <&clock 132>;
87 clock-names = "biu", "ciu";
91 reset-names = "reset";
92 vmmc-supply = <&buck8>;
99 card-detect-delay = <200>;
100 max-frequency = <200000000>;
101 clock-frequency = <400000000>;
104 fifo-watermark-aligned;