1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI AM654 MMC Controller
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - const: ti,am654-sdhci-5.1
20 - const: ti,j721e-sdhci-8bit
21 - const: ti,j721e-sdhci-4bit
22 - const: ti,j721e-sdhci-4bit
23 - const: ti,am64-sdhci-8bit
24 - const: ti,am64-sdhci-4bit
26 - const: ti,j7200-sdhci-8bit
27 - const: ti,j721e-sdhci-8bit
29 - const: ti,j7200-sdhci-4bit
30 - const: ti,j721e-sdhci-4bit
44 description: Handles to input clocks
53 # PHY output tap delays:
54 # Used to delay the data valid window and align it to the sampling clock.
55 # Binding needs to be provided for each supported speed mode otherwise the
56 # corresponding mode will be disabled.
58 ti,otap-del-sel-legacy:
59 description: Output tap delay for SD/MMC legacy timing
60 $ref: "/schemas/types.yaml#/definitions/uint32"
64 ti,otap-del-sel-mmc-hs:
65 description: Output tap delay for MMC high speed timing
66 $ref: "/schemas/types.yaml#/definitions/uint32"
70 ti,otap-del-sel-sd-hs:
71 description: Output tap delay for SD high speed timing
72 $ref: "/schemas/types.yaml#/definitions/uint32"
76 ti,otap-del-sel-sdr12:
77 description: Output tap delay for SD UHS SDR12 timing
78 $ref: "/schemas/types.yaml#/definitions/uint32"
82 ti,otap-del-sel-sdr25:
83 description: Output tap delay for SD UHS SDR25 timing
84 $ref: "/schemas/types.yaml#/definitions/uint32"
88 ti,otap-del-sel-sdr50:
89 description: Output tap delay for SD UHS SDR50 timing
90 $ref: "/schemas/types.yaml#/definitions/uint32"
94 ti,otap-del-sel-sdr104:
95 description: Output tap delay for SD UHS SDR104 timing
96 $ref: "/schemas/types.yaml#/definitions/uint32"
100 ti,otap-del-sel-ddr50:
101 description: Output tap delay for SD UHS DDR50 timing
102 $ref: "/schemas/types.yaml#/definitions/uint32"
106 ti,otap-del-sel-ddr52:
107 description: Output tap delay for eMMC DDR52 timing
108 $ref: "/schemas/types.yaml#/definitions/uint32"
112 ti,otap-del-sel-hs200:
113 description: Output tap delay for eMMC HS200 timing
114 $ref: "/schemas/types.yaml#/definitions/uint32"
118 ti,otap-del-sel-hs400:
119 description: Output tap delay for eMMC HS400 timing
120 $ref: "/schemas/types.yaml#/definitions/uint32"
124 # PHY input tap delays:
125 # Used to delay the data valid window and align it to the sampling clock for
126 # modes that don't support tuning
128 ti,itap-del-sel-legacy:
129 description: Input tap delay for SD/MMC legacy timing
130 $ref: "/schemas/types.yaml#/definitions/uint32"
134 ti,itap-del-sel-mmc-hs:
135 description: Input tap delay for MMC high speed timing
136 $ref: "/schemas/types.yaml#/definitions/uint32"
140 ti,itap-del-sel-sd-hs:
141 description: Input tap delay for SD high speed timing
142 $ref: "/schemas/types.yaml#/definitions/uint32"
146 ti,itap-del-sel-sdr12:
147 description: Input tap delay for SD UHS SDR12 timing
148 $ref: "/schemas/types.yaml#/definitions/uint32"
152 ti,itap-del-sel-sdr25:
153 description: Input tap delay for SD UHS SDR25 timing
154 $ref: "/schemas/types.yaml#/definitions/uint32"
158 ti,itap-del-sel-ddr52:
159 description: Input tap delay for MMC DDR52 timing
160 $ref: "/schemas/types.yaml#/definitions/uint32"
165 description: DLL trim select
166 $ref: "/schemas/types.yaml#/definitions/uint32"
170 ti,driver-strength-ohm:
171 description: DLL drive strength in ohms
172 $ref: "/schemas/types.yaml#/definitions/uint32"
181 description: strobe select delay for HS400 speed mode.
182 $ref: "/schemas/types.yaml#/definitions/uint32"
185 description: Clock Delay Buffer Select
186 $ref: "/schemas/types.yaml#/definitions/uint32"
194 - ti,otap-del-sel-legacy
196 unevaluatedProperties: false
200 #include <dt-bindings/interrupt-controller/irq.h>
201 #include <dt-bindings/interrupt-controller/arm-gic.h>
204 #address-cells = <2>;
208 compatible = "ti,am654-sdhci-5.1";
209 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
210 power-domains = <&k3_pds 47>;
211 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
212 clock-names = "clk_ahb", "clk_xin";
213 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
214 sdhci-caps-mask = <0x80000007 0x0>;
216 ti,otap-del-sel-legacy = <0x0>;
217 ti,otap-del-sel-mmc-hs = <0x0>;
218 ti,otap-del-sel-ddr52 = <0x5>;
219 ti,otap-del-sel-hs200 = <0x5>;
220 ti,otap-del-sel-hs400 = <0x0>;
221 ti,itap-del-sel-legacy = <0x10>;
222 ti,itap-del-sel-mmc-hs = <0xa>;
223 ti,itap-del-sel-ddr52 = <0x3>;