1 * NVIDIA Tegra Secure Digital Host Controller
3 This controller on Tegra family SoCs provides an interface for MMC, SD,
4 and SDIO types of memory cards.
6 This file documents differences between the core properties described
7 by mmc.txt and the properties used by the sdhci-tegra driver.
10 - compatible : should be one of:
11 - "nvidia,tegra20-sdhci": for Tegra20
12 - "nvidia,tegra30-sdhci": for Tegra30
13 - "nvidia,tegra114-sdhci": for Tegra114
14 - "nvidia,tegra124-sdhci": for Tegra124 and Tegra132
15 - "nvidia,tegra210-sdhci": for Tegra210
16 - "nvidia,tegra186-sdhci": for Tegra186
17 - "nvidia,tegra194-sdhci": for Tegra194
18 - clocks: For Tegra210, Tegra186 and Tegra194 must contain two entries.
19 One for the module clock and one for the timeout clock.
20 For all other Tegra devices, must contain a single entry for
21 the module clock. See ../clocks/clock-bindings.txt for details.
22 - clock-names: For Tegra210, Tegra186 and Tegra194 must contain the
23 strings 'sdhci' and 'tmclk' to represent the module and
24 the timeout clocks, respectively.
25 For all other Tegra devices must contain the string 'sdhci'
26 to represent the module clock.
27 - resets : Must contain an entry for each entry in reset-names.
28 See ../reset/reset.txt for details.
29 - reset-names : Must include the following entries:
33 - power-gpios : Specify GPIOs for power control
38 compatible = "nvidia,tegra20-sdhci";
39 reg = <0xc8000200 0x200>;
41 clocks = <&tegra_car 14>;
42 resets = <&tegra_car 14>;
43 reset-names = "sdhci";
44 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
45 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
46 power-gpios = <&gpio 155 0>; /* gpio PT3 */
50 Optional properties for Tegra210, Tegra186 and Tegra194:
51 - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
52 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
53 for controllers supporting multiple voltage levels. The order of names
54 should correspond to the pin configuration states in pinctrl-0 and
56 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
57 Tegra210 where pad config registers are in the pinmux register domain
58 for pull-up-strength and pull-down-strength values configuration when
59 using pads at 3V3 and 1V8 levels.
60 - nvidia,only-1-8-v : The presence of this property indicates that the
61 controller operates at a 1.8 V fixed I/O voltage.
62 - nvidia,pad-autocal-pull-up-offset-3v3,
63 nvidia,pad-autocal-pull-down-offset-3v3 : Specify drive strength
64 calibration offsets for 3.3 V signaling modes.
65 - nvidia,pad-autocal-pull-up-offset-1v8,
66 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
67 calibration offsets for 1.8 V signaling modes.
68 - nvidia,pad-autocal-pull-up-offset-3v3-timeout,
69 nvidia,pad-autocal-pull-down-offset-3v3-timeout : Specify drive
70 strength used as a fallback in case the automatic calibration times
71 out on a 3.3 V signaling mode.
72 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
73 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
74 strength used as a fallback in case the automatic calibration times
75 out on a 1.8 V signaling mode.
76 - nvidia,pad-autocal-pull-up-offset-sdr104,
77 nvidia,pad-autocal-pull-down-offset-sdr104 : Specify drive strength
78 calibration offsets for SDR104 mode.
79 - nvidia,pad-autocal-pull-up-offset-hs400,
80 nvidia,pad-autocal-pull-down-offset-hs400 : Specify drive strength
81 calibration offsets for HS400 mode.
82 - nvidia,default-tap : Specify the default inbound sampling clock
83 trimmer value for non-tunable modes.
84 - nvidia,default-trim : Specify the default outbound clock trimmer
86 - nvidia,dqs-trim : Specify DQS trim value for HS400 timing
88 Notes on the pad calibration pull up and pulldown offset values:
89 - The property values are drive codes which are programmed into the
90 PD_OFFSET and PU_OFFSET sections of the
91 SDHCI_TEGRA_AUTO_CAL_CONFIG register.
92 - A higher value corresponds to higher drive strength. Please refer
93 to the reference manual of the SoC for correct values.
94 - The SDR104 and HS400 timing specific values are used in
95 corresponding modes if specified.
97 Notes on tap and trim values:
98 - The values are used for compensating trace length differences
99 by adjusting the sampling point.
100 - The values are programmed to the Vendor Clock Control Register.
101 Please refer to the reference manual of the SoC for correct
103 - The DQS trim values are only used on controllers which support
104 HS400 timing. Only SDMMC4 on Tegra210 and Tegra 186 supports
109 compatible = "nvidia,tegra124-sdhci";
110 reg = <0x0 0x700b0000 0x0 0x200>;
111 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
113 clock-names = "sdhci";
114 resets = <&tegra_car 14>;
115 reset-names = "sdhci";
116 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
117 pinctrl-0 = <&sdmmc1_3v3>;
118 pinctrl-1 = <&sdmmc1_1v8>;
119 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
120 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
121 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
122 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
127 compatible = "nvidia,tegra210-sdhci";
128 reg = <0x0 0x700b0000 0x0 0x200>;
129 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
131 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
132 clock-names = "sdhci", "tmclk";
133 resets = <&tegra_car 14>;
134 reset-names = "sdhci";
135 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
136 pinctrl-0 = <&sdmmc1_3v3>;
137 pinctrl-1 = <&sdmmc1_1v8>;
138 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
139 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
140 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
141 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;