1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MTK MSDC Storage Host Controller
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
29 - const: mediatek,mt7623-mmc
30 - const: mediatek,mt2701-mmc
38 - const: mediatek,mt8183-mmc
43 - description: base register (required).
44 - description: top base register (required for MT8183).
48 Should contain phandle for the clock feeding the MMC controller.
58 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
59 interrupt is required and be configured as wakeup source irq.
70 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
71 will be switched between GPIO mode and SDIO DAT1 mode, state_eint is mandatory in this
81 should contain default/high speed pin ctrl.
86 should contain uhs mode pin ctrl.
91 should switch dat1 pin to GPIO mode.
95 $ref: /schemas/types.yaml#/definitions/uint32
97 HS400 DS delay setting.
101 mediatek,hs200-cmd-int-delay:
102 $ref: /schemas/types.yaml#/definitions/uint32
104 HS200 command internal delay setting.
105 This field has total 32 stages.
106 The value is an integer from 0 to 31.
110 mediatek,hs400-cmd-int-delay:
111 $ref: /schemas/types.yaml#/definitions/uint32
113 HS400 command internal delay setting.
114 This field has total 32 stages.
115 The value is an integer from 0 to 31.
119 mediatek,hs400-cmd-resp-sel-rising:
120 $ref: /schemas/types.yaml#/definitions/flag
122 HS400 command response sample selection.
123 If present, HS400 command responses are sampled on rising edges.
124 If not present, HS400 command responses are sampled on falling edges.
126 mediatek,hs400-ds-dly3:
127 $ref: /schemas/types.yaml#/definitions/uint32
129 Gear of the third delay line for DS for input data latch in data
130 pad macro, there are 32 stages from 0 to 31.
131 For different corner IC, the time is different about one step, it is
133 The value is confirmed by doing scan and calibration to find a best
134 value with corner IC and it is valid only for HS400 mode.
139 $ref: /schemas/types.yaml#/definitions/uint32
141 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
142 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
143 if not present, default value is 0.
144 applied to compatible "mediatek,mt2701-mmc".
148 mediatek,tuning-step:
149 $ref: /schemas/types.yaml#/definitions/uint32
151 Some SoCs need extend tuning step for better delay value to avoid CRC issue.
152 If not present, default tuning step is 32. For eMMC and SD, this can yield
153 satisfactory calibration results in most cases.
176 - $ref: mmc-controller.yaml#
181 - mediatek,mt2701-mmc
182 - mediatek,mt6779-mmc
183 - mediatek,mt6795-mmc
184 - mediatek,mt7620-mmc
185 - mediatek,mt7622-mmc
186 - mediatek,mt7623-mmc
187 - mediatek,mt8135-mmc
188 - mediatek,mt8173-mmc
189 - mediatek,mt8183-mmc
190 - mediatek,mt8186-mmc
191 - mediatek,mt8188-mmc
192 - mediatek,mt8195-mmc
193 - mediatek,mt8516-mmc
199 - description: source clock
200 - description: HCLK which used for host
201 - description: independent source clock gate
213 const: mediatek,mt2712-mmc
219 - description: source clock
220 - description: HCLK which used for host
221 - description: independent source clock gate
222 - description: bus clock used for internal register access (required for MSDC0/3).
235 const: mediatek,mt8183-mmc
246 - mediatek,mt7986-mmc
252 - description: source clock
253 - description: HCLK which used for host
254 - description: independent source clock gate
255 - description: bus clock used for internal register access (required for MSDC0/3).
256 - description: msdc subsys clock gate
270 - mediatek,mt8186-mmc
271 - mediatek,mt8188-mmc
272 - mediatek,mt8195-mmc
277 - description: source clock
278 - description: HCLK which used for host
279 - description: independent source clock gate
280 - description: crypto clock used for data encrypt/decrypt (optional)
292 const: mediatek,mt8192-mmc
297 - description: source clock
298 - description: HCLK which used for host
299 - description: independent source clock gate
300 - description: msdc subsys clock gate
301 - description: peripheral bus clock gate
302 - description: AXI bus clock gate
303 - description: AHB bus clock gate
314 unevaluatedProperties: false
318 #include <dt-bindings/interrupt-controller/irq.h>
319 #include <dt-bindings/interrupt-controller/arm-gic.h>
320 #include <dt-bindings/clock/mt8173-clk.h>
322 compatible = "mediatek,mt8173-mmc";
323 reg = <0x11230000 0x1000>;
324 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
325 vmmc-supply = <&mt6397_vemc_3v3_reg>;
326 vqmmc-supply = <&mt6397_vio18_reg>;
327 clocks = <&pericfg CLK_PERI_MSDC30_0>,
328 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
329 clock-names = "source", "hclk";
330 pinctrl-names = "default", "state_uhs";
331 pinctrl-0 = <&mmc0_pins_default>;
332 pinctrl-1 = <&mmc0_pins_uhs>;
333 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
334 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
335 hs400-ds-delay = <0x14015>;
336 mediatek,hs200-cmd-int-delay = <26>;
337 mediatek,hs400-cmd-int-delay = <14>;
338 mediatek,hs400-cmd-resp-sel-rising;
342 compatible = "mediatek,mt8173-mmc";
343 reg = <0x11260000 0x1000>;
344 clock-names = "source", "hclk";
345 clocks = <&pericfg CLK_PERI_MSDC30_3>,
346 <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
347 interrupt-names = "msdc", "sdio_wakeup";
348 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
349 <&pio 23 IRQ_TYPE_LEVEL_LOW>;
350 pinctrl-names = "default", "state_uhs", "state_eint";
351 pinctrl-0 = <&mmc2_pins_default>;
352 pinctrl-1 = <&mmc2_pins_uhs>;
353 pinctrl-2 = <&mmc2_pins_eint>;
355 max-frequency = <200000000>;
358 keep-power-in-suspend;
364 vmmc-supply = <&sdio_fixed_3v3>;
365 vqmmc-supply = <&mt6397_vgp3_reg>;
366 mmc-pwrseq = <&wifi_pwrseq>;