1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MTK MSDC Storage Host Controller Binding
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
30 - const: mediatek,mt7623-mmc
31 - const: mediatek,mt2701-mmc
33 - const: mediatek,mt8192-mmc
34 - const: mediatek,mt8195-mmc
35 - const: mediatek,mt8183-mmc
39 Should contain phandle for the clock feeding the MMC controller.
42 - description: source clock (required).
43 - description: HCLK which used for host (required).
44 - description: independent source clock gate (required for MT2712).
45 - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
46 - description: msdc subsys clock gate (required for MT8192).
47 - description: peripheral bus clock gate (required for MT8192).
48 - description: AXI bus clock gate (required for MT8192).
49 - description: AHB bus clock gate (required for MT8192).
70 should contain default/high speed pin ctrl.
75 should contain uhs mode pin ctrl.
80 PLL of the source clock.
83 assigned-clock-parents:
85 parent of source clock, used for HS400 mode to get 400Mhz source clock.
89 $ref: /schemas/types.yaml#/definitions/uint32
91 HS400 DS delay setting.
95 mediatek,hs200-cmd-int-delay:
96 $ref: /schemas/types.yaml#/definitions/uint32
98 HS200 command internal delay setting.
99 This field has total 32 stages.
100 The value is an integer from 0 to 31.
104 mediatek,hs400-cmd-int-delay:
105 $ref: /schemas/types.yaml#/definitions/uint32
107 HS400 command internal delay setting.
108 This field has total 32 stages.
109 The value is an integer from 0 to 31.
113 mediatek,hs400-cmd-resp-sel-rising:
114 $ref: /schemas/types.yaml#/definitions/flag
116 HS400 command response sample selection.
117 If present, HS400 command responses are sampled on rising edges.
118 If not present, HS400 command responses are sampled on falling edges.
121 $ref: /schemas/types.yaml#/definitions/uint32
123 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
124 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
125 if not present, default value is 0.
126 applied to compatible "mediatek,mt2701-mmc".
148 unevaluatedProperties: false
152 #include <dt-bindings/interrupt-controller/irq.h>
153 #include <dt-bindings/interrupt-controller/arm-gic.h>
154 #include <dt-bindings/clock/mt8173-clk.h>
156 compatible = "mediatek,mt8173-mmc";
157 reg = <0x11230000 0x1000>;
158 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
159 vmmc-supply = <&mt6397_vemc_3v3_reg>;
160 vqmmc-supply = <&mt6397_vio18_reg>;
161 clocks = <&pericfg CLK_PERI_MSDC30_0>,
162 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
163 clock-names = "source", "hclk";
164 pinctrl-names = "default", "state_uhs";
165 pinctrl-0 = <&mmc0_pins_default>;
166 pinctrl-1 = <&mmc0_pins_uhs>;
167 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
168 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
169 hs400-ds-delay = <0x14015>;
170 mediatek,hs200-cmd-int-delay = <26>;
171 mediatek,hs400-cmd-int-delay = <14>;
172 mediatek,hs400-cmd-resp-sel-rising;