1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Common Properties
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 These properties are common to multiple MMC host controllers. Any host
14 that requires the respective functionality should implement them using
17 It is possible to assign a fixed index mmcN to an MMC host controller
18 (and the corresponding mmcblkN devices) by defining an alias in the
19 /aliases device tree node.
23 pattern: "^mmc(@.*)?$"
28 The cell is the slot ID if a function subnode is used.
34 # If none of these properties are supplied, the host native card
35 # detect will be used. Only one of them should be provided.
38 $ref: /schemas/types.yaml#/definitions/flag
40 There is no card detection available; polling must be used.
45 The card detection will be done using the GPIO provided.
48 $ref: /schemas/types.yaml#/definitions/flag
50 Non-removable slot (like eMMC); assume always present.
52 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host
53 # controllers line polarity properties, we have to fix the meaning
54 # of the "normal" and "inverted" line levels. We choose to follow
55 # the SDHCI standard, which specifies both those lines as "active
56 # low." Therefore, using the "cd-inverted" property means, that the
57 # CD line is active high, i.e. it is high, when a card is
58 # inserted. Similar logic applies to the "wp-inverted" property.
60 # CD and WP lines can be implemented on the hardware in one of two
61 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or
62 # as dedicated pins. Polarity of dedicated pins can be specified,
63 # using *-inverted properties. GPIO polarity can also be specified
64 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the
65 # latter case. We choose to use the XOR logic for GPIO CD and WP
66 # lines. This means, the two properties are "superimposed," for
67 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the
68 # respective *-inverted property property results in a
69 # double-inversion and actually means the "normal" line polarity is
72 $ref: /schemas/types.yaml#/definitions/flag
74 The Write Protect line polarity is inverted.
77 $ref: /schemas/types.yaml#/definitions/flag
79 The CD line polarity is inverted.
86 $ref: /schemas/types.yaml#/definitions/uint32
92 Maximum operating frequency of the bus:
93 - for eMMC, the maximum supported frequency is 200MHz,
94 - for SD/SDIO cards the SDR104 mode has a max supported
96 - some mmc host controllers do support a max frequency upto
98 So, lets keep the maximum supported value here.
100 $ref: /schemas/types.yaml#/definitions/uint32
105 $ref: /schemas/types.yaml#/definitions/flag
107 When set, no physical write-protect line is present. This
108 property should only be specified when the controller has a
109 dedicated write-protect detection logic. If a GPIO is always used
110 for the write-protect detection logic, it is sufficient to not
111 specify the wp-gpios property in the absence of a write-protect
112 line. Not used in combination with eMMC or SDIO.
117 GPIO to use for the write-protect detection.
119 cd-debounce-delay-ms:
121 Set delay time before detecting card after card insert
125 $ref: /schemas/types.yaml#/definitions/flag
127 When specified, denotes that 1.8V card voltage is not supported
128 on this system, even if the controller claims it.
131 $ref: /schemas/types.yaml#/definitions/flag
133 SD high-speed timing is supported.
136 $ref: /schemas/types.yaml#/definitions/flag
138 MMC high-speed timing is supported.
141 $ref: /schemas/types.yaml#/definitions/flag
143 SD UHS SDR12 speed is supported.
146 $ref: /schemas/types.yaml#/definitions/flag
148 SD UHS SDR25 speed is supported.
151 $ref: /schemas/types.yaml#/definitions/flag
153 SD UHS SDR50 speed is supported.
156 $ref: /schemas/types.yaml#/definitions/flag
158 SD UHS SDR104 speed is supported.
161 $ref: /schemas/types.yaml#/definitions/flag
163 SD UHS DDR50 speed is supported.
166 $ref: /schemas/types.yaml#/definitions/flag
168 Powering off the card is safe.
171 $ref: /schemas/types.yaml#/definitions/flag
173 eMMC hardware reset is supported
176 $ref: /schemas/types.yaml#/definitions/flag
178 enable SDIO IRQ signalling on this interface
181 $ref: /schemas/types.yaml#/definitions/flag
183 Full power cycle of the card is supported.
185 full-pwr-cycle-in-suspend:
186 $ref: /schemas/types.yaml#/definitions/flag
188 Full power cycle of the card in suspend is supported.
191 $ref: /schemas/types.yaml#/definitions/flag
193 eMMC high-speed DDR mode (1.2V I/O) is supported.
196 $ref: /schemas/types.yaml#/definitions/flag
198 eMMC high-speed DDR mode (1.8V I/O) is supported.
201 $ref: /schemas/types.yaml#/definitions/flag
203 eMMC high-speed DDR mode (3.3V I/O) is supported.
206 $ref: /schemas/types.yaml#/definitions/flag
208 eMMC HS200 mode (1.2V I/O) is supported.
211 $ref: /schemas/types.yaml#/definitions/flag
213 eMMC HS200 mode (1.8V I/O) is supported.
216 $ref: /schemas/types.yaml#/definitions/flag
218 eMMC HS400 mode (1.2V I/O) is supported.
221 $ref: /schemas/types.yaml#/definitions/flag
223 eMMC HS400 mode (1.8V I/O) is supported.
225 mmc-hs400-enhanced-strobe:
226 $ref: /schemas/types.yaml#/definitions/flag
228 eMMC HS400 enhanced strobe mode is supported
231 $ref: /schemas/types.yaml#/definitions/flag
233 All eMMC HS400 modes are not supported.
237 Value the card Driver Stage Register (DSR) should be programmed
239 $ref: /schemas/types.yaml#/definitions/uint32
244 $ref: /schemas/types.yaml#/definitions/flag
246 Controller is limited to send SDIO commands during
250 $ref: /schemas/types.yaml#/definitions/flag
252 Controller is limited to send SD commands during initialization.
255 $ref: /schemas/types.yaml#/definitions/flag
257 Controller is limited to send MMC commands during
260 fixed-emmc-driver-type:
262 For non-removable eMMC, enforce this driver type. The value is
263 the driver type as specified in the eMMC specification (table
264 206 in spec version 5.1)
265 $ref: /schemas/types.yaml#/definitions/uint32
269 post-power-on-delay-ms:
271 It was invented for MMC pwrseq-simple which could be referred to
272 mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay
273 waiting for I/O signalling and card power supply to be stable,
274 regardless of whether pwrseq-simple is used. Default to 10ms if
279 $ref: /schemas/types.yaml#/definitions/flag
281 The presence of this property indicates that the corresponding
282 MMC host controller supports HW command queue feature.
285 $ref: /schemas/types.yaml#/definitions/flag
287 The presence of this property indicates that the MMC
288 controller\'s command queue engine (CQE) does not support direct
291 keep-power-in-suspend:
292 $ref: /schemas/types.yaml#/definitions/flag
294 SDIO only. Preserves card power during a suspend/resume cycle.
297 $ref: /schemas/types.yaml#/definitions/flag
299 SDIO only. Enables wake up of host system on SDIO IRQ assertion.
303 Supply for the card power
307 Supply for the bus IO line power, such as a level shifter.
308 If the level shifter is controlled by a GPIO line, this shall
309 be modeled as a "regulator-fixed" with a GPIO line for
310 switching the level shifter on/off.
313 $ref: /schemas/types.yaml#/definitions/phandle
315 System-on-Chip designs may specify a specific MMC power
316 sequence. To successfully detect an (e)MMC/SD/SDIO card, that
317 power sequence must be maintained while initializing the card.
323 On embedded systems the cards connected to a host may need
324 additional properties. These can be specified in subnodes to the
325 host controller node. The subnodes are identified by the
326 standard \'reg\' property. Which information exactly can be
327 specified depends on the bindings for the SDIO function driver
328 for the subnode, as specified by the compatible string.
333 Name of SDIO function following generic names recommended
341 Must contain the SDIO function number of the function this
342 subnode describes. A value of 0 denotes the memory SD
343 function, values from 1 to 7 denote the SDIO functions.
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
349 $ref: /schemas/types.yaml#/definitions/uint32-array
357 Set the clock (phase) delays which are to be configured in the
358 controller while switching to particular speed mode. These values
359 are in pair of degrees.
362 cd-debounce-delay-ms: [ cd-gpios ]
363 fixed-emmc-driver-type: [ non-removable ]
365 additionalProperties: true
370 #address-cells = <1>;
372 reg = <0x1c12000 0x200>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&mmc3_pins_a>;
375 vmmc-supply = <®_vmmc3>;
378 mmc-pwrseq = <&sdhci0_pwrseq>;
382 compatible = "brcm,bcm4329-fmac";
383 interrupt-parent = <&pio>;
385 interrupt-names = "host-wake";