1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
34 # PHY DLL input delays:
35 # They are used to delay the data valid window, and align the window to
36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37 # and it is increased by 2.5ns in each step.
39 cdns,phy-input-delay-sd-highspeed:
40 description: Value of the delay in the input path for SD high-speed timing
41 $ref: /schemas/types.yaml#/definitions/uint32
45 cdns,phy-input-delay-legacy:
46 description: Value of the delay in the input path for legacy timing
47 $ref: /schemas/types.yaml#/definitions/uint32
51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the input path for SD UHS SDR12 timing
53 $ref: /schemas/types.yaml#/definitions/uint32
57 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the input path for SD UHS SDR25 timing
59 $ref: /schemas/types.yaml#/definitions/uint32
63 cdns,phy-input-delay-sd-uhs-sdr50:
64 description: Value of the delay in the input path for SD UHS SDR50 timing
65 $ref: /schemas/types.yaml#/definitions/uint32
69 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the input path for SD UHS DDR50 timing
71 $ref: /schemas/types.yaml#/definitions/uint32
75 cdns,phy-input-delay-mmc-highspeed:
76 description: Value of the delay in the input path for MMC high-speed timing
77 $ref: /schemas/types.yaml#/definitions/uint32
81 cdns,phy-input-delay-mmc-ddr:
82 description: Value of the delay in the input path for eMMC high-speed DDR timing
84 # PHY DLL clock delays:
85 # Each delay property represents the fraction of the clock period.
86 # The approximate delay value will be
87 # (<delay property value>/128)*sdmclk_clock_period.
88 $ref: /schemas/types.yaml#/definitions/uint32
92 cdns,phy-dll-delay-sdclk:
94 Value of the delay introduced on the sdclk output for all modes except
95 HS200, HS400 and HS400_ES.
96 $ref: /schemas/types.yaml#/definitions/uint32
100 cdns,phy-dll-delay-sdclk-hsmmc:
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
103 HS400_ES speed modes.
104 $ref: /schemas/types.yaml#/definitions/uint32
108 cdns,phy-dll-delay-strobe:
110 Value of the delay introduced on the dat_strobe input used in
111 HS400 / HS400_ES speed modes.
112 $ref: /schemas/types.yaml#/definitions/uint32
123 - $ref: mmc-controller.yaml
128 const: amd,pensando-elba-sd4hc
133 - description: Host controller registers
134 - description: Elba byte-lane enable register for writes
142 unevaluatedProperties: false
147 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
148 reg = <0x5a000000 0x400>;
149 interrupts = <0 78 4>;
155 cdns,phy-dll-delay-sdclk = <0>;