1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mmc/arm,pl18x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PrimeCell MultiMedia Card Interface (MMCI) PL180 and PL181
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 The ARM PrimeCells MMCI PL180 and PL181 provides an interface for
15 reading and writing to MultiMedia and SD cards alike. Over the years
16 vendors have use the VHDL code from ARM to create derivative MMC/SD/SDIO
17 host controllers with very similar characteristics.
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
23 # We need a select here so we don't match all nodes with 'arm,primecell'
38 - description: The first version of the block, simply called
39 PL180 and found in the ARM Integrator IM/PD1 logic module.
42 - const: arm,primecell
43 - description: The improved version of the block, found in the
44 ARM Versatile and later reference designs. Further revisions
45 exist but get detected at runtime by reading some magic numbers
46 in the PrimeCell ID registers.
49 - const: arm,primecell
50 - description: Wildcard entry that will let the operating system
51 inspect the PrimeCell ID registers to determine which hardware
52 variant of PL180 or PL181 this is.
55 - const: arm,primecell
58 description: One or two clocks, the "apb_pclk" and the "MCLK"
59 which is the core block clock. The names are not compulsory.
69 description: the MMIO memory window must be exactly 4KB (0x1000) and the
70 layout should provide the PrimeCell ID registers so that the device can
71 be discovered. On ST Micro variants, a second register window may be
72 defined if a delay block is present and used for tuning.
75 description: The first interrupt is the command interrupt and corresponds
76 to the event at the end of a command. The second interrupt is the
77 PIO (polled I/O) interrupt and occurs when the FIFO needs to be
78 emptied as part of a bulk read from the card. Some variants have these
79 two interrupts wired into the same line (logic OR) and in that case
80 only one interrupt may be provided.
85 $ref: /schemas/types.yaml#/definitions/flag
86 description: ST Micro-specific property, bus signal direction pins used for
90 $ref: /schemas/types.yaml#/definitions/flag
91 description: ST Micro-specific property, bus signal direction pins used for
95 $ref: /schemas/types.yaml#/definitions/flag
96 description: ST Micro-specific property, bus signal direction pins used for
100 $ref: /schemas/types.yaml#/definitions/flag
101 description: ST Micro-specific property, bus signal direction pins used for
105 $ref: /schemas/types.yaml#/definitions/flag
106 description: ST Micro-specific property, CMD signal direction used for
110 $ref: /schemas/types.yaml#/definitions/flag
111 description: ST Micro-specific property, feedback clock FBCLK signal pin
115 $ref: /schemas/types.yaml#/definitions/flag
116 description: ST Micro-specific property, signal direction polarity used for
117 pins CMD, DAT[0], DAT[1], DAT[2] and DAT[3].
120 $ref: /schemas/types.yaml#/definitions/flag
121 description: ST Micro-specific property, data and command phase relation,
122 generated on the sd clock falling edge.
125 $ref: /schemas/types.yaml#/definitions/flag
126 description: ST Micro-specific property, use CKIN pin from an external
127 driver to sample the receive data (for example with a voltage switch
133 The GPIO matching the CMD pin.
138 The GPIO matching the CK pin.
143 The GPIO matching the CKIN pin.
146 st,cmd-gpios: [ "st,use-ckin" ]
147 st,ck-gpios: [ "st,use-ckin" ]
148 st,ckin-gpios: [ "st,use-ckin" ]
150 unevaluatedProperties: false
159 #include <dt-bindings/interrupt-controller/irq.h>
160 #include <dt-bindings/gpio/gpio.h>
163 compatible = "arm,pl180", "arm,primecell";
164 reg = <0x5000 0x1000>;
165 interrupts-extended = <&vic 22 &sic 1>;
166 clocks = <&xtal24mhz>, <&pclk>;
167 clock-names = "mclk", "apb_pclk";
171 compatible = "arm,pl18x", "arm,primecell";
172 reg = <0x80126000 0x1000>;
173 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
174 dmas = <&dma 29 0 0x2>, <&dma 29 0 0x0>;
175 dma-names = "rx", "tx";
176 clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
177 clock-names = "sdi", "apb_pclk";
178 max-frequency = <100000000>;
182 cd-gpios = <&gpio2 31 0x4>;
187 vmmc-supply = <&ab8500_ldo_aux3_reg>;
188 vqmmc-supply = <&vmmci>;
192 compatible = "arm,pl18x", "arm,primecell";
193 reg = <0x101f6000 0x1000>;
194 clocks = <&sdiclk>, <&pclksdi>;
195 clock-names = "mclk", "apb_pclk";
196 interrupt-parent = <&vica>;
198 max-frequency = <400000>;
208 vmmc-supply = <&vmmc_regulator>;
212 compatible = "arm,pl18x", "arm,primecell";
213 arm,primecell-periphid = <0x10153180>;
214 reg = <0x52007000 0x1000>;
216 interrupt-names = "cmd_irq";
218 clock-names = "apb_pclk";
222 max-frequency = <120000000>;