1 Device Tree Bindings for the Arasan SDHCI Controller
3 The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
4 Only deviations are documented here.
6 [1] Documentation/devicetree/bindings/mmc/mmc.txt
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - reg: From mmc bindings: Register location and length.
19 - clocks: From clock bindings: Handles to clock inputs.
20 - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
21 - interrupts: Interrupt specifier
22 - interrupt-parent: Phandle for the interrupt controller that services
23 interrupts for this device.
25 Required Properties for "arasan,sdhci-5.1":
26 - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
27 - phy-names: MUST be "phy_arasan".
30 - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
31 used to access core corecfg registers. Offsets of registers in this
32 syscon are determined based on the main compatible string for the device.
33 - clock-output-names: If specified, this will be the name of the card clock
34 which will be exposed by this device. Required if #clock-cells is
36 - #clock-cells: If specified this should be the value <0>. With this property
37 in place we will export a clock representing the Card Clock. This clock
38 is expected to be consumed by our PHY. You must also specify
42 compatible = "arasan,sdhci-8.9a";
43 reg = <0xe0100000 0x1000>;
44 clock-names = "clk_xin", "clk_ahb";
45 clocks = <&clkc 21>, <&clkc 32>;
46 interrupt-parent = <&gic>;
47 interrupts = <0 24 4>;
51 compatible = "arasan,sdhci-5.1";
52 reg = <0xe2800000 0x1000>;
53 clock-names = "clk_xin", "clk_ahb";
54 clocks = <&cru 8>, <&cru 18>;
55 interrupt-parent = <&gic>;
56 interrupts = <0 24 4>;
58 phy-names = "phy_arasan";
61 sdhci: sdhci@fe330000 {
62 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
63 reg = <0x0 0xfe330000 0x0 0x10000>;
64 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
65 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
66 clock-names = "clk_xin", "clk_ahb";
67 arasan,soc-ctl-syscon = <&grf>;
68 assigned-clocks = <&cru SCLK_EMMC>;
69 assigned-clock-rates = <200000000>;
70 clock-output-names = "emmc_cardclock";
72 phy-names = "phy_arasan";