Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

   1 Device Tree Bindings for the Arasan SDHCI Controller
   2
   3   The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
   4   Only deviations are documented here.
   5
   6   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   7   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   8   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
   9   [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
  10
  11 Required Properties:
  12   - compatible: Compatibility string.  One of:
  13     - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
  14     - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
  15     - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
  16     - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
  17       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  18     - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
  19       For this device it is strongly suggested to include clock-output-names and
  20       #clock-cells.
  21     - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
  22       For this device it is strongly suggested to include clock-output-names and
  23       #clock-cells.
  24     - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
  25         Note: This binding has been deprecated and moved to [5].
  26     - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
  27       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  28     - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
  29       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  30     - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
  31       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  32     - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
  33       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  34     - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
  35       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  36
  37   [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
  38
  39   - reg: From mmc bindings: Register location and length.
  40   - clocks: From clock bindings: Handles to clock inputs.
  41   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  42   - interrupts: Interrupt specifier
  43
  44 Required Properties for "arasan,sdhci-5.1":
  45   - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  46   - phy-names:  MUST be "phy_arasan".
  47
  48 Optional Properties:
  49   - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
  50     used to access core corecfg registers.  Offsets of registers in this
  51     syscon are determined based on the main compatible string for the device.
  52   - clock-output-names: If specified, this will be the name of the card clock
  53     which will be exposed by this device.  Required if #clock-cells is
  54     specified.
  55   - #clock-cells: If specified this should be the value <0> or <1>. With this
  56     property in place we will export one or two clocks representing the Card
  57     Clock. These clocks are expected to be consumed by our PHY.
  58   - xlnx,fails-without-test-cd: when present, the controller doesn't work when
  59     the CD line is not connected properly, and the line is not connected
  60     properly. Test mode can be used to force the controller to function.
  61   - xlnx,int-clock-stable-broken: when present, the controller always reports
  62     that the internal clock is stable even when it is not.
  63
  64   - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
  65     which the command and data lines are configured. If not specified, driver
  66     will assume this as 0.
  67
  68 Example:
  69         sdhci@e0100000 {
  70                 compatible = "arasan,sdhci-8.9a";
  71                 reg = <0xe0100000 0x1000>;
  72                 clock-names = "clk_xin", "clk_ahb";
  73                 clocks = <&clkc 21>, <&clkc 32>;
  74                 interrupt-parent = <&gic>;
  75                 interrupts = <0 24 4>;
  76         } ;
  77
  78         sdhci@e2800000 {
  79                 compatible = "arasan,sdhci-5.1";
  80                 reg = <0xe2800000 0x1000>;
  81                 clock-names = "clk_xin", "clk_ahb";
  82                 clocks = <&cru 8>, <&cru 18>;
  83                 interrupt-parent = <&gic>;
  84                 interrupts = <0 24 4>;
  85                 phys = <&emmc_phy>;
  86                 phy-names = "phy_arasan";
  87         } ;
  88
  89         sdhci: sdhci@fe330000 {
  90                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  91                 reg = <0x0 0xfe330000 0x0 0x10000>;
  92                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  93                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
  94                 clock-names = "clk_xin", "clk_ahb";
  95                 arasan,soc-ctl-syscon = <&grf>;
  96                 assigned-clocks = <&cru SCLK_EMMC>;
  97                 assigned-clock-rates = <200000000>;
  98                 clock-output-names = "emmc_cardclock";
  99                 phys = <&emmc_phy>;
 100                 phy-names = "phy_arasan";
 101                 #clock-cells = <0>;
 102         };
 103
 104         sdhci: mmc@ff160000 {
 105                 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 106                 interrupt-parent = <&gic>;
 107                 interrupts = <0 48 4>;
 108                 reg = <0x0 0xff160000 0x0 0x1000>;
 109                 clocks = <&clk200>, <&clk200>;
 110                 clock-names = "clk_xin", "clk_ahb";
 111                 clock-output-names = "clk_out_sd0", "clk_in_sd0";
 112                 #clock-cells = <1>;
 113                 clk-phase-sd-hs = <63>, <72>;
 114         };
 115
 116         sdhci: mmc@f1040000 {
 117                 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
 118                 interrupt-parent = <&gic>;
 119                 interrupts = <0 126 4>;
 120                 reg = <0x0 0xf1040000 0x0 0x10000>;
 121                 clocks = <&clk200>, <&clk200>;
 122                 clock-names = "clk_xin", "clk_ahb";
 123                 clock-output-names = "clk_out_sd0", "clk_in_sd0";
 124                 #clock-cells = <1>;
 125                 clk-phase-sd-hs = <132>, <60>;
 126         };
 127
 128         emmc: sdhci@ec700000 {
 129                 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
 130                 reg = <0xec700000 0x300>;
 131                 interrupt-parent = <&ioapic1>;
 132                 interrupts = <44 1>;
 133                 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
 134                          <&cgu0 LGM_GCLK_EMMC>;
 135                 clock-names = "clk_xin", "clk_ahb", "gate";
 136                 clock-output-names = "emmc_cardclock";
 137                 #clock-cells = <0>;
 138                 phys = <&emmc_phy>;
 139                 phy-names = "phy_arasan";
 140                 arasan,soc-ctl-syscon = <&sysconf>;
 141         };
 142
 143         sdxc: sdhci@ec600000 {
 144                 compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
 145                 reg = <0xec600000 0x300>;
 146                 interrupt-parent = <&ioapic1>;
 147                 interrupts = <43 1>;
 148                 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
 149                          <&cgu0 LGM_GCLK_SDXC>;
 150                 clock-names = "clk_xin", "clk_ahb", "gate";
 151                 clock-output-names = "sdxc_cardclock";
 152                 #clock-cells = <0>;
 153                 phys = <&sdxc_phy>;
 154                 phy-names = "phy_arasan";
 155                 arasan,soc-ctl-syscon = <&sysconf>;
 156         };
 157
 158         mmc: mmc@33000000 {
 159                 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
 160                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 161                 reg = <0x0 0x33000000 0x0 0x300>;
 162                 clock-names = "clk_xin", "clk_ahb";
 163                 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
 164                          <&scmi_clk KEEM_BAY_PSS_EMMC>;
 165                 phys = <&emmc_phy>;
 166                 phy-names = "phy_arasan";
 167                 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
 168                 assigned-clock-rates = <200000000>;
 169                 clock-output-names = "emmc_cardclock";
 170                 #clock-cells = <0>;
 171                 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
 172         };
 173
 174         sd0: mmc@31000000 {
 175                 compatible = "intel,keembay-sdhci-5.1-sd";
 176                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 177                 reg = <0x0 0x31000000 0x0 0x300>;
 178                 clock-names = "clk_xin", "clk_ahb";
 179                 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
 180                          <&scmi_clk KEEM_BAY_PSS_SD0>;
 181                 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
 182         };
 183
 184         sd1: mmc@32000000 {
 185                 compatible = "intel,keembay-sdhci-5.1-sdio";
 186                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 187                 reg = <0x0 0x32000000 0x0 0x300>;
 188                 clock-names = "clk_xin", "clk_ahb";
 189                 clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
 190                          <&scmi_clk KEEM_BAY_PSS_SD1>;
 191                 arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
 192         };