1 Device Tree Bindings for the Arasan SDHCI Controller
3 The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
4 Only deviations are documented here.
6 [1] Documentation/devicetree/bindings/mmc/mmc.txt
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
19 For this device it is strongly suggested to include clock-output-names and
21 - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
22 For this device it is strongly suggested to include clock-output-names and
24 - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
25 Note: This binding has been deprecated and moved to [5].
26 - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
27 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
28 - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
29 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
31 [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
33 - reg: From mmc bindings: Register location and length.
34 - clocks: From clock bindings: Handles to clock inputs.
35 - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
36 - interrupts: Interrupt specifier
38 Required Properties for "arasan,sdhci-5.1":
39 - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
40 - phy-names: MUST be "phy_arasan".
43 - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
44 used to access core corecfg registers. Offsets of registers in this
45 syscon are determined based on the main compatible string for the device.
46 - clock-output-names: If specified, this will be the name of the card clock
47 which will be exposed by this device. Required if #clock-cells is
49 - #clock-cells: If specified this should be the value <0> or <1>. With this
50 property in place we will export one or two clocks representing the Card
51 Clock. These clocks are expected to be consumed by our PHY.
52 - xlnx,fails-without-test-cd: when present, the controller doesn't work when
53 the CD line is not connected properly, and the line is not connected
54 properly. Test mode can be used to force the controller to function.
55 - xlnx,int-clock-stable-broken: when present, the controller always reports
56 that the internal clock is stable even when it is not.
58 - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
59 which the command and data lines are configured. If not specified, driver
60 will assume this as 0.
64 compatible = "arasan,sdhci-8.9a";
65 reg = <0xe0100000 0x1000>;
66 clock-names = "clk_xin", "clk_ahb";
67 clocks = <&clkc 21>, <&clkc 32>;
68 interrupt-parent = <&gic>;
69 interrupts = <0 24 4>;
73 compatible = "arasan,sdhci-5.1";
74 reg = <0xe2800000 0x1000>;
75 clock-names = "clk_xin", "clk_ahb";
76 clocks = <&cru 8>, <&cru 18>;
77 interrupt-parent = <&gic>;
78 interrupts = <0 24 4>;
80 phy-names = "phy_arasan";
83 sdhci: sdhci@fe330000 {
84 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
85 reg = <0x0 0xfe330000 0x0 0x10000>;
86 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
87 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
88 clock-names = "clk_xin", "clk_ahb";
89 arasan,soc-ctl-syscon = <&grf>;
90 assigned-clocks = <&cru SCLK_EMMC>;
91 assigned-clock-rates = <200000000>;
92 clock-output-names = "emmc_cardclock";
94 phy-names = "phy_arasan";
99 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
100 interrupt-parent = <&gic>;
101 interrupts = <0 48 4>;
102 reg = <0x0 0xff160000 0x0 0x1000>;
103 clocks = <&clk200>, <&clk200>;
104 clock-names = "clk_xin", "clk_ahb";
105 clock-output-names = "clk_out_sd0", "clk_in_sd0";
107 clk-phase-sd-hs = <63>, <72>;
110 sdhci: mmc@f1040000 {
111 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
112 interrupt-parent = <&gic>;
113 interrupts = <0 126 4>;
114 reg = <0x0 0xf1040000 0x0 0x10000>;
115 clocks = <&clk200>, <&clk200>;
116 clock-names = "clk_xin", "clk_ahb";
117 clock-output-names = "clk_out_sd0", "clk_in_sd0";
119 clk-phase-sd-hs = <132>, <60>;
122 emmc: sdhci@ec700000 {
123 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
124 reg = <0xec700000 0x300>;
125 interrupt-parent = <&ioapic1>;
127 clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
128 <&cgu0 LGM_GCLK_EMMC>;
129 clock-names = "clk_xin", "clk_ahb", "gate";
130 clock-output-names = "emmc_cardclock";
133 phy-names = "phy_arasan";
134 arasan,soc-ctl-syscon = <&sysconf>;
137 sdxc: sdhci@ec600000 {
138 compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
139 reg = <0xec600000 0x300>;
140 interrupt-parent = <&ioapic1>;
142 clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
143 <&cgu0 LGM_GCLK_SDXC>;
144 clock-names = "clk_xin", "clk_ahb", "gate";
145 clock-output-names = "sdxc_cardclock";
148 phy-names = "phy_arasan";
149 arasan,soc-ctl-syscon = <&sysconf>;