1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
10 - Álvaro Fernández Rojas <noltari@gmail.com>
11 - Jonas Gorski <jonas.gorski@gmail.com>
14 Broadcom BCM63268 SoC GPIO system controller which provides a register map
15 for controlling the GPIO and pins of the SoC.
18 "#address-cells": true
24 - const: brcm,bcm63268-gpio-sysctl
38 $ref: "../gpio/brcm,bcm6345-gpio.yaml"
40 GPIO controller for the SoC GPIOs. This child node definition
41 should follow the bindings specified in
42 Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
44 "^pinctrl@[0-9a-f]+$":
47 $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
49 Pin controller for the SoC pins. This child node definition
50 should follow the bindings specified in
51 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
60 additionalProperties: false
67 compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
68 reg = <0x100000c0 0x80>;
69 ranges = <0 0x100000c0 0x80>;
72 compatible = "brcm,bcm63268-gpio";
73 reg-names = "dirout", "dat";
74 reg = <0x0 0x8>, <0x8 0x8>;
77 gpio-ranges = <&pinctrl 0 0 52>;
82 compatible = "brcm,bcm63268-pinctrl";
83 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
85 pinctrl_serial_led: serial_led-pins {
86 pinctrl_serial_led_clk: serial_led_clk-pins {
87 function = "serial_led_clk";
91 pinctrl_serial_led_data: serial_led_data-pins {
92 function = "serial_led_data";
97 pinctrl_hsspi_cs4: hsspi_cs4-pins {
98 function = "hsspi_cs4";
102 pinctrl_hsspi_cs5: hsspi_cs5-pins {
103 function = "hsspi_cs5";
107 pinctrl_hsspi_cs6: hsspi_cs6-pins {
108 function = "hsspi_cs6";
112 pinctrl_hsspi_cs7: hsspi_cs7-pins {
113 function = "hsspi_cs7";
117 pinctrl_adsl_spi: adsl_spi-pins {
118 pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
119 function = "adsl_spi_miso";
123 pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
124 function = "adsl_spi_mosi";
129 pinctrl_vreq_clk: vreq_clk-pins {
130 function = "vreq_clk";
134 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
135 function = "pcie_clkreq_b";
139 pinctrl_robosw_led_clk: robosw_led_clk-pins {
140 function = "robosw_led_clk";
144 pinctrl_robosw_led_data: robosw_led_data-pins {
145 function = "robosw_led_data";
149 pinctrl_nand: nand-pins {
154 pinctrl_gpio35_alt: gpio35_alt-pins {
155 function = "gpio35_alt";
159 pinctrl_dectpd: dectpd-pins {
161 group = "dectpd_grp";
164 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
165 function = "vdsl_phy_override_0";
166 group = "vdsl_phy_override_0_grp";
169 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
170 function = "vdsl_phy_override_1";
171 group = "vdsl_phy_override_1_grp";
174 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
175 function = "vdsl_phy_override_2";
176 group = "vdsl_phy_override_2_grp";
179 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
180 function = "vdsl_phy_override_3";
181 group = "vdsl_phy_override_3_grp";
184 pinctrl_dsl_gpio8: dsl_gpio8-pins {
185 function = "dsl_gpio8";
189 pinctrl_dsl_gpio9: dsl_gpio9-pins {
190 function = "dsl_gpio9";