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2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
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5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
6 peripheral devices, replacing the use of the ISA bus in the age of PCI[0]. The
7 primary use case of the Aspeed LPC controller is as a slave on the bus
8 (typically in a Baseboard Management Controller SoC), but under certain
9 conditions it can also take the role of bus master.
11 The LPC controller is represented as a multi-function device to account for the
12 mix of functionality, which includes, but is not limited to:
14 * An IPMI Block Transfer[2] Controller
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
17 physical properties of some LPC pins, configuration of serial IRQs, and
18 APB-to-LPC bridging amonst other functions.
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
22 management and bus snoop configuration.
24 * A set of SuperIO[3] scratch registers: Enables implementation of e.g. custom
25 hardware management protocols for handover between the host and baseboard
26 management controller.
28 Additionally the state of the LPC controller influences the pinmux
29 configuration, therefore the host portion of the controller is exposed as a
30 syscon as a means to arbitrate access.
32 [0] http://www.intel.com/design/chipsets/industry/25128901.pdf
33 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c88837454702128622bee53acbda8f4
34 [2] https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
35 [3] https://en.wikipedia.org/wiki/Super_I/O
41 "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
42 "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
43 "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
45 - reg: contains the physical address and length values of the Aspeed
50 - ranges: Maps 0 to the physical address and length of the LPC memory
56 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
57 reg = <0x1e789000 0x1000>;
61 ranges = <0x0 0x1e789000 0x1000>;
63 lpc_snoop: lpc-snoop@0 {
64 compatible = "aspeed,ast2600-lpc-snoop";
66 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
72 LPC Host Interface Controller
75 The LPC Host Interface Controller manages functions exposed to the host such as
76 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
77 management and bus snoop configuration.
82 "aspeed,ast2400-lpc-ctrl";
83 "aspeed,ast2500-lpc-ctrl";
84 "aspeed,ast2600-lpc-ctrl";
86 - reg: contains offset/length values of the host interface controller
89 - clocks: contains a phandle to the syscon node describing the clocks.
90 There should then be one cell representing the clock to use
94 - memory-region: A phandle to a reserved_memory region to be used for the LPC
97 - flash: A phandle to the SPI flash controller containing the flash to
98 be exposed over the LPC to AHB mapping
102 lpc_ctrl: lpc-ctrl@80 {
103 compatible = "aspeed,ast2500-lpc-ctrl";
105 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
106 memory-region = <&flash_memory>;
113 The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
114 between the host and the baseboard management controller. The registers exist
115 in the "host" portion of the Aspeed LPC controller, which must be the parent of
116 the LPC host controller node.
120 - compatible: One of:
121 "aspeed,ast2400-lhc";
122 "aspeed,ast2500-lhc";
123 "aspeed,ast2600-lhc";
125 - reg: contains offset/length values of the LHC memory regions. In the
126 AST2400 and AST2500 there are two regions.
131 compatible = "aspeed,ast2500-lhc";
132 reg = <0xa0 0x24 0xc8 0x8>;
138 The UARTs present in the ASPEED SoC can have their resets tied to the reset
139 state of the LPC bus. Some systems may chose to modify this configuration.
143 - compatible: One of:
144 "aspeed,ast2600-lpc-reset";
145 "aspeed,ast2500-lpc-reset";
146 "aspeed,ast2400-lpc-reset";
148 - reg: offset and length of the IP in the LHC memory region
149 - #reset-controller indicates the number of reset cells expected
153 lpc_reset: reset-controller@98 {
154 compatible = "aspeed,ast2500-lpc-reset";