1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra124 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra124-emc
26 - description: external memory clock
32 nvidia,memory-controller:
33 $ref: /schemas/types.yaml#/definitions/phandle
35 phandle of the memory controller node
38 "^emc-timings-[0-9]+$":
42 $ref: /schemas/types.yaml#/definitions/uint32
44 value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
45 this timing set is used for
53 external memory clock rate in Hz
57 nvidia,emc-auto-cal-config:
58 $ref: /schemas/types.yaml#/definitions/uint32
60 value of the EMC_AUTO_CAL_CONFIG register for this set of
63 nvidia,emc-auto-cal-config2:
64 $ref: /schemas/types.yaml#/definitions/uint32
66 value of the EMC_AUTO_CAL_CONFIG2 register for this set of
69 nvidia,emc-auto-cal-config3:
70 $ref: /schemas/types.yaml#/definitions/uint32
72 value of the EMC_AUTO_CAL_CONFIG3 register for this set of
75 nvidia,emc-auto-cal-interval:
77 pad calibration interval in microseconds
78 $ref: /schemas/types.yaml#/definitions/uint32
82 nvidia,emc-bgbias-ctl0:
83 $ref: /schemas/types.yaml#/definitions/uint32
85 value of the EMC_BGBIAS_CTL0 register for this set of timings
88 $ref: /schemas/types.yaml#/definitions/uint32
90 value of the EMC_CFG register for this set of timings
93 $ref: /schemas/types.yaml#/definitions/uint32
95 value of the EMC_CFG_2 register for this set of timings
97 nvidia,emc-ctt-term-ctrl:
98 $ref: /schemas/types.yaml#/definitions/uint32
100 value of the EMC_CTT_TERM_CTRL register for this set of timings
103 $ref: /schemas/types.yaml#/definitions/uint32
105 value of the EMC_MRW register for this set of timings
108 $ref: /schemas/types.yaml#/definitions/uint32
110 value of the EMC_MRW2 register for this set of timings
113 $ref: /schemas/types.yaml#/definitions/uint32
115 value of the EMC_MRW4 register for this set of timings
117 nvidia,emc-mode-reset:
118 $ref: /schemas/types.yaml#/definitions/uint32
120 reset value of the EMC_MRS register for this set of timings
122 nvidia,emc-mrs-wait-cnt:
123 $ref: /schemas/types.yaml#/definitions/uint32
125 value of the EMR_MRS_WAIT_CNT register for this set of timings
127 nvidia,emc-sel-dpd-ctrl:
128 $ref: /schemas/types.yaml#/definitions/uint32
130 value of the EMC_SEL_DPD_CTRL register for this set of timings
132 nvidia,emc-xm2dqspadctrl2:
133 $ref: /schemas/types.yaml#/definitions/uint32
135 value of the EMC_XM2DQSPADCTRL2 register for this set of timings
137 nvidia,emc-zcal-cnt-long:
139 number of EMC clocks to wait before issuing any commands after
141 $ref: /schemas/types.yaml#/definitions/uint32
145 nvidia,emc-zcal-interval:
146 $ref: /schemas/types.yaml#/definitions/uint32
148 value of the EMC_ZCAL_INTERVAL register for this set of timings
150 nvidia,emc-configuration:
152 EMC timing characterization data. These are the registers (see
153 section "15.6.2 EMC Registers" in the TRM) whose values need to
154 be specified, according to the board documentation.
155 $ref: /schemas/types.yaml#/definitions/uint32-array
157 - description: EMC_RC
158 - description: EMC_RFC
159 - description: EMC_RFC_SLR
160 - description: EMC_RAS
161 - description: EMC_RP
162 - description: EMC_R2W
163 - description: EMC_W2R
164 - description: EMC_R2P
165 - description: EMC_W2P
166 - description: EMC_RD_RCD
167 - description: EMC_WR_RCD
168 - description: EMC_RRD
169 - description: EMC_REXT
170 - description: EMC_WEXT
171 - description: EMC_WDV
172 - description: EMC_WDV_MASK
173 - description: EMC_QUSE
174 - description: EMC_QUSE_WIDTH
175 - description: EMC_IBDLY
176 - description: EMC_EINPUT
177 - description: EMC_EINPUT_DURATION
178 - description: EMC_PUTERM_EXTRA
179 - description: EMC_PUTERM_WIDTH
180 - description: EMC_PUTERM_ADJ
181 - description: EMC_CDB_CNTL_1
182 - description: EMC_CDB_CNTL_2
183 - description: EMC_CDB_CNTL_3
184 - description: EMC_QRST
185 - description: EMC_QSAFE
186 - description: EMC_RDV
187 - description: EMC_RDV_MASK
188 - description: EMC_REFRESH
189 - description: EMC_BURST_REFRESH_NUM
190 - description: EMC_PRE_REFRESH_REQ_CNT
191 - description: EMC_PDEX2WR
192 - description: EMC_PDEX2RD
193 - description: EMC_PCHG2PDEN
194 - description: EMC_ACT2PDEN
195 - description: EMC_AR2PDEN
196 - description: EMC_RW2PDEN
197 - description: EMC_TXSR
198 - description: EMC_TXSRDLL
199 - description: EMC_TCKE
200 - description: EMC_TCKESR
201 - description: EMC_TPD
202 - description: EMC_TFAW
203 - description: EMC_TRPAB
204 - description: EMC_TCLKSTABLE
205 - description: EMC_TCLKSTOP
206 - description: EMC_TREFBW
207 - description: EMC_FBIO_CFG6
208 - description: EMC_ODT_WRITE
209 - description: EMC_ODT_READ
210 - description: EMC_FBIO_CFG5
211 - description: EMC_CFG_DIG_DLL
212 - description: EMC_CFG_DIG_DLL_PERIOD
213 - description: EMC_DLL_XFORM_DQS0
214 - description: EMC_DLL_XFORM_DQS1
215 - description: EMC_DLL_XFORM_DQS2
216 - description: EMC_DLL_XFORM_DQS3
217 - description: EMC_DLL_XFORM_DQS4
218 - description: EMC_DLL_XFORM_DQS5
219 - description: EMC_DLL_XFORM_DQS6
220 - description: EMC_DLL_XFORM_DQS7
221 - description: EMC_DLL_XFORM_DQS8
222 - description: EMC_DLL_XFORM_DQS9
223 - description: EMC_DLL_XFORM_DQS10
224 - description: EMC_DLL_XFORM_DQS11
225 - description: EMC_DLL_XFORM_DQS12
226 - description: EMC_DLL_XFORM_DQS13
227 - description: EMC_DLL_XFORM_DQS14
228 - description: EMC_DLL_XFORM_DQS15
229 - description: EMC_DLL_XFORM_QUSE0
230 - description: EMC_DLL_XFORM_QUSE1
231 - description: EMC_DLL_XFORM_QUSE2
232 - description: EMC_DLL_XFORM_QUSE3
233 - description: EMC_DLL_XFORM_QUSE4
234 - description: EMC_DLL_XFORM_QUSE5
235 - description: EMC_DLL_XFORM_QUSE6
236 - description: EMC_DLL_XFORM_QUSE7
237 - description: EMC_DLL_XFORM_ADDR0
238 - description: EMC_DLL_XFORM_ADDR1
239 - description: EMC_DLL_XFORM_ADDR2
240 - description: EMC_DLL_XFORM_ADDR3
241 - description: EMC_DLL_XFORM_ADDR4
242 - description: EMC_DLL_XFORM_ADDR5
243 - description: EMC_DLL_XFORM_QUSE8
244 - description: EMC_DLL_XFORM_QUSE9
245 - description: EMC_DLL_XFORM_QUSE10
246 - description: EMC_DLL_XFORM_QUSE11
247 - description: EMC_DLL_XFORM_QUSE12
248 - description: EMC_DLL_XFORM_QUSE13
249 - description: EMC_DLL_XFORM_QUSE14
250 - description: EMC_DLL_XFORM_QUSE15
251 - description: EMC_DLI_TRIM_TXDQS0
252 - description: EMC_DLI_TRIM_TXDQS1
253 - description: EMC_DLI_TRIM_TXDQS2
254 - description: EMC_DLI_TRIM_TXDQS3
255 - description: EMC_DLI_TRIM_TXDQS4
256 - description: EMC_DLI_TRIM_TXDQS5
257 - description: EMC_DLI_TRIM_TXDQS6
258 - description: EMC_DLI_TRIM_TXDQS7
259 - description: EMC_DLI_TRIM_TXDQS8
260 - description: EMC_DLI_TRIM_TXDQS9
261 - description: EMC_DLI_TRIM_TXDQS10
262 - description: EMC_DLI_TRIM_TXDQS11
263 - description: EMC_DLI_TRIM_TXDQS12
264 - description: EMC_DLI_TRIM_TXDQS13
265 - description: EMC_DLI_TRIM_TXDQS14
266 - description: EMC_DLI_TRIM_TXDQS15
267 - description: EMC_DLL_XFORM_DQ0
268 - description: EMC_DLL_XFORM_DQ1
269 - description: EMC_DLL_XFORM_DQ2
270 - description: EMC_DLL_XFORM_DQ3
271 - description: EMC_DLL_XFORM_DQ4
272 - description: EMC_DLL_XFORM_DQ5
273 - description: EMC_DLL_XFORM_DQ6
274 - description: EMC_DLL_XFORM_DQ7
275 - description: EMC_XM2CMDPADCTRL
276 - description: EMC_XM2CMDPADCTRL4
277 - description: EMC_XM2CMDPADCTRL5
278 - description: EMC_XM2DQPADCTRL2
279 - description: EMC_XM2DQPADCTRL3
280 - description: EMC_XM2CLKPADCTRL
281 - description: EMC_XM2CLKPADCTRL2
282 - description: EMC_XM2COMPPADCTRL
283 - description: EMC_XM2VTTGENPADCTRL
284 - description: EMC_XM2VTTGENPADCTRL2
285 - description: EMC_XM2VTTGENPADCTRL3
286 - description: EMC_XM2DQSPADCTRL3
287 - description: EMC_XM2DQSPADCTRL4
288 - description: EMC_XM2DQSPADCTRL5
289 - description: EMC_XM2DQSPADCTRL6
290 - description: EMC_DSR_VTTGEN_DRV
291 - description: EMC_TXDSRVTTGEN
292 - description: EMC_FBIO_SPARE
293 - description: EMC_ZCAL_WAIT_CNT
294 - description: EMC_MRS_WAIT_CNT2
295 - description: EMC_CTT
296 - description: EMC_CTT_DURATION
297 - description: EMC_CFG_PIPE
298 - description: EMC_DYN_SELF_REF_CONTROL
299 - description: EMC_QPOP
303 - nvidia,emc-auto-cal-config
304 - nvidia,emc-auto-cal-config2
305 - nvidia,emc-auto-cal-config3
306 - nvidia,emc-auto-cal-interval
307 - nvidia,emc-bgbias-ctl0
310 - nvidia,emc-ctt-term-ctrl
314 - nvidia,emc-mode-reset
315 - nvidia,emc-mrs-wait-cnt
316 - nvidia,emc-sel-dpd-ctrl
317 - nvidia,emc-xm2dqspadctrl2
318 - nvidia,emc-zcal-cnt-long
319 - nvidia,emc-zcal-interval
320 - nvidia,emc-configuration
322 additionalProperties: false
329 - nvidia,memory-controller
331 additionalProperties: false
335 #include <dt-bindings/clock/tegra124-car.h>
336 #include <dt-bindings/interrupt-controller/arm-gic.h>
338 mc: memory-controller@70019000 {
339 compatible = "nvidia,tegra124-mc";
340 reg = <0x70019000 0x1000>;
341 clocks = <&tegra_car TEGRA124_CLK_MC>;
344 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
350 external-memory-controller@7001b000 {
351 compatible = "nvidia,tegra124-emc";
352 reg = <0x7001b000 0x1000>;
353 clocks = <&car TEGRA124_CLK_EMC>;
356 nvidia,memory-controller = <&mc>;
359 nvidia,ram-code = <3>;
362 clock-frequency = <12750000>;
364 nvidia,emc-auto-cal-config = <0xa1430000>;
365 nvidia,emc-auto-cal-config2 = <0x00000000>;
366 nvidia,emc-auto-cal-config3 = <0x00000000>;
367 nvidia,emc-auto-cal-interval = <0x001fffff>;
368 nvidia,emc-bgbias-ctl0 = <0x00000008>;
369 nvidia,emc-cfg = <0x73240000>;
370 nvidia,emc-cfg-2 = <0x000008c5>;
371 nvidia,emc-ctt-term-ctrl = <0x00000802>;
372 nvidia,emc-mode-1 = <0x80100003>;
373 nvidia,emc-mode-2 = <0x80200008>;
374 nvidia,emc-mode-4 = <0x00000000>;
375 nvidia,emc-mode-reset = <0x80001221>;
376 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
377 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
378 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
379 nvidia,emc-zcal-cnt-long = <0x00000042>;
380 nvidia,emc-zcal-interval = <0x00000000>;
382 nvidia,emc-configuration = <
383 0x00000000 /* EMC_RC */
384 0x00000003 /* EMC_RFC */
385 0x00000000 /* EMC_RFC_SLR */
386 0x00000000 /* EMC_RAS */
387 0x00000000 /* EMC_RP */
388 0x00000004 /* EMC_R2W */
389 0x0000000a /* EMC_W2R */
390 0x00000003 /* EMC_R2P */
391 0x0000000b /* EMC_W2P */
392 0x00000000 /* EMC_RD_RCD */
393 0x00000000 /* EMC_WR_RCD */
394 0x00000003 /* EMC_RRD */
395 0x00000003 /* EMC_REXT */
396 0x00000000 /* EMC_WEXT */
397 0x00000006 /* EMC_WDV */
398 0x00000006 /* EMC_WDV_MASK */
399 0x00000006 /* EMC_QUSE */
400 0x00000002 /* EMC_QUSE_WIDTH */
401 0x00000000 /* EMC_IBDLY */
402 0x00000005 /* EMC_EINPUT */
403 0x00000005 /* EMC_EINPUT_DURATION */
404 0x00010000 /* EMC_PUTERM_EXTRA */
405 0x00000003 /* EMC_PUTERM_WIDTH */
406 0x00000000 /* EMC_PUTERM_ADJ */
407 0x00000000 /* EMC_CDB_CNTL_1 */
408 0x00000000 /* EMC_CDB_CNTL_2 */
409 0x00000000 /* EMC_CDB_CNTL_3 */
410 0x00000004 /* EMC_QRST */
411 0x0000000c /* EMC_QSAFE */
412 0x0000000d /* EMC_RDV */
413 0x0000000f /* EMC_RDV_MASK */
414 0x00000060 /* EMC_REFRESH */
415 0x00000000 /* EMC_BURST_REFRESH_NUM */
416 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
417 0x00000002 /* EMC_PDEX2WR */
418 0x00000002 /* EMC_PDEX2RD */
419 0x00000001 /* EMC_PCHG2PDEN */
420 0x00000000 /* EMC_ACT2PDEN */
421 0x00000007 /* EMC_AR2PDEN */
422 0x0000000f /* EMC_RW2PDEN */
423 0x00000005 /* EMC_TXSR */
424 0x00000005 /* EMC_TXSRDLL */
425 0x00000004 /* EMC_TCKE */
426 0x00000005 /* EMC_TCKESR */
427 0x00000004 /* EMC_TPD */
428 0x00000000 /* EMC_TFAW */
429 0x00000000 /* EMC_TRPAB */
430 0x00000005 /* EMC_TCLKSTABLE */
431 0x00000005 /* EMC_TCLKSTOP */
432 0x00000064 /* EMC_TREFBW */
433 0x00000000 /* EMC_FBIO_CFG6 */
434 0x00000000 /* EMC_ODT_WRITE */
435 0x00000000 /* EMC_ODT_READ */
436 0x106aa298 /* EMC_FBIO_CFG5 */
437 0x002c00a0 /* EMC_CFG_DIG_DLL */
438 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
439 0x00064000 /* EMC_DLL_XFORM_DQS0 */
440 0x00064000 /* EMC_DLL_XFORM_DQS1 */
441 0x00064000 /* EMC_DLL_XFORM_DQS2 */
442 0x00064000 /* EMC_DLL_XFORM_DQS3 */
443 0x00064000 /* EMC_DLL_XFORM_DQS4 */
444 0x00064000 /* EMC_DLL_XFORM_DQS5 */
445 0x00064000 /* EMC_DLL_XFORM_DQS6 */
446 0x00064000 /* EMC_DLL_XFORM_DQS7 */
447 0x00064000 /* EMC_DLL_XFORM_DQS8 */
448 0x00064000 /* EMC_DLL_XFORM_DQS9 */
449 0x00064000 /* EMC_DLL_XFORM_DQS10 */
450 0x00064000 /* EMC_DLL_XFORM_DQS11 */
451 0x00064000 /* EMC_DLL_XFORM_DQS12 */
452 0x00064000 /* EMC_DLL_XFORM_DQS13 */
453 0x00064000 /* EMC_DLL_XFORM_DQS14 */
454 0x00064000 /* EMC_DLL_XFORM_DQS15 */
455 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
456 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
457 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
458 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
459 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
460 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
461 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
462 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
463 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
464 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
465 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
466 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
467 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
468 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
469 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
470 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
471 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
472 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
473 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
474 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
475 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
476 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
477 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
478 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
479 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
480 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
481 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
482 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
483 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
484 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
485 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
486 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
487 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
488 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
489 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
490 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
491 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
492 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
493 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
494 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
495 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
496 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
497 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
498 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
499 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
500 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
501 0x10000280 /* EMC_XM2CMDPADCTRL */
502 0x00000000 /* EMC_XM2CMDPADCTRL4 */
503 0x00111111 /* EMC_XM2CMDPADCTRL5 */
504 0x00000000 /* EMC_XM2DQPADCTRL2 */
505 0x00000000 /* EMC_XM2DQPADCTRL3 */
506 0x77ffc081 /* EMC_XM2CLKPADCTRL */
507 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
508 0x81f1f108 /* EMC_XM2COMPPADCTRL */
509 0x07070004 /* EMC_XM2VTTGENPADCTRL */
510 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
511 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
512 0x51451400 /* EMC_XM2DQSPADCTRL3 */
513 0x00514514 /* EMC_XM2DQSPADCTRL4 */
514 0x00514514 /* EMC_XM2DQSPADCTRL5 */
515 0x51451400 /* EMC_XM2DQSPADCTRL6 */
516 0x0000003f /* EMC_DSR_VTTGEN_DRV */
517 0x00000007 /* EMC_TXDSRVTTGEN */
518 0x00000000 /* EMC_FBIO_SPARE */
519 0x00000042 /* EMC_ZCAL_WAIT_CNT */
520 0x000e000e /* EMC_MRS_WAIT_CNT2 */
521 0x00000000 /* EMC_CTT */
522 0x00000003 /* EMC_CTT_DURATION */
523 0x0000f2f3 /* EMC_CFG_PIPE */
524 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
525 0x0000000a /* EMC_QPOP */