1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
15 representation of DRIF interfacing with a master device is shown below.
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
20 | |-----SD0------->|D0 |
21 | |-----SD1------->|D1 |
22 +---------------------+ +---------------------+
24 As per datasheet, each DRIF channel (drifn) is made up of two internal
25 channels (drifn0 & drifn1). These two internal channels share the common
26 CLK & SYNC. Each internal channel has its own dedicated resources like
27 irq, dma channels, address space & clock. This internal split is not
28 visible to the external master device.
30 The device tree model represents each internal channel as a separate node.
31 The internal channels sharing the CLK & SYNC are tied together by their
32 phandles using a property called "renesas,bonding". For the rest of
33 the documentation, unless explicitly stated, the word channel implies an
36 When both internal channels are enabled they need to be managed together
37 as one (i.e.) they cannot operate alone as independent devices. Out of the
38 two, one of them needs to act as a primary device that accepts common
39 properties of both the internal channels. This channel is identified by a
40 property called "renesas,primary-bond".
43 * When both the internal channels that are bonded together are enabled,
44 the zeroth channel is selected as primary-bond. This channels accepts
45 properties common to all the members of the bond.
46 * When only one of the bonded channels need to be enabled, the property
47 "renesas,bonding" or "renesas,primary-bond" will have no effect. That
48 enabled channel can act alone as any other independent device.
54 - renesas,r8a7795-drif # R-Car H3
55 - renesas,r8a7796-drif # R-Car M3-W
56 - renesas,r8a77965-drif # R-Car M3-N
57 - renesas,r8a77990-drif # R-Car E3
58 - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
89 $ref: /schemas/types.yaml#/definitions/phandle
91 The phandle to the other internal channel of DRIF
99 Indicates that the channel acts as primary among the bonded channels.
104 Child port node corresponding to the data input, in accordance with the
105 video interface bindings defined in
106 Documentation/devicetree/bindings/media/video-interfaces.txt.
107 The port node must contain at least one endpoint.
116 A phandle to the remote tuner endpoint subnode in remote node
122 Indicates sync signal polarity, 0/1 for low/high respectively.
123 This property maps to SYNCAC bit in the hardware manual. The
124 default is 1 (active high).
126 additionalProperties: false
143 - renesas,primary-bond
162 additionalProperties: false
165 # Example with both internal channels enabled.
167 # When interfacing with a third party tuner device with two data pins as shown
170 # +---------------------+ +---------------------+
171 # | |-----SCK------->|CLK |
172 # | Master |-----SS-------->|SYNC DRIFn (slave) |
173 # | |-----SD0------->|D0 |
174 # | |-----SD1------->|D1 |
175 # +---------------------+ +---------------------+
177 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
178 #include <dt-bindings/interrupt-controller/arm-gic.h>
179 #include <dt-bindings/power/r8a7795-sysc.h>
182 #address-cells = <2>;
185 drif00: rif@e6f40000 {
186 compatible = "renesas,r8a7795-drif",
187 "renesas,rcar-gen3-drif";
188 reg = <0 0xe6f40000 0 0x64>;
189 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&cpg CPG_MOD 515>;
192 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
193 dma-names = "rx", "rx";
194 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
195 renesas,bonding = <&drif01>;
197 renesas,primary-bond;
198 pinctrl-0 = <&drif0_pins>;
199 pinctrl-names = "default";
202 remote-endpoint = <&tuner_ep>;
207 drif01: rif@e6f50000 {
208 compatible = "renesas,r8a7795-drif",
209 "renesas,rcar-gen3-drif";
210 reg = <0 0xe6f50000 0 0x64>;
211 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cpg CPG_MOD 514>;
214 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
215 dma-names = "rx", "rx";
216 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
217 renesas,bonding = <&drif00>;
222 # Example with internal channel 1 alone enabled.
224 # When interfacing with a third party tuner device with one data pin as shown
227 # +---------------------+ +---------------------+
228 # | |-----SCK------->|CLK |
229 # | Master |-----SS-------->|SYNC DRIFn (slave) |
231 # | |-----SD-------->|D1 |
232 # +---------------------+ +---------------------+
234 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
235 #include <dt-bindings/interrupt-controller/arm-gic.h>
236 #include <dt-bindings/power/r8a7795-sysc.h>
239 #address-cells = <2>;
242 drif10: rif@e6f60000 {
243 compatible = "renesas,r8a7795-drif",
244 "renesas,rcar-gen3-drif";
245 reg = <0 0xe6f60000 0 0x64>;
246 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&cpg CPG_MOD 513>;
249 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
250 dma-names = "rx", "rx";
251 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
253 renesas,bonding = <&drif11>;
257 drif11: rif@e6f70000 {
258 compatible = "renesas,r8a7795-drif",
259 "renesas,rcar-gen3-drif";
260 reg = <0 0xe6f70000 0 0x64>;
261 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&cpg CPG_MOD 512>;
264 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
265 dma-names = "rx", "rx";
266 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
268 renesas,bonding = <&drif10>;
269 pinctrl-0 = <&drif1_pins>;
270 pinctrl-names = "default";
273 remote-endpoint = <&tuner_ep1>;