Documentation/devicetree/bindings/media/renesas,drif.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
   8
   9 maintainers:
  10   - Ramesh Shanmugasundaram <rashanmu@gmail.com>
  11   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
  12
  13 description: |
  14   R-Car Gen3 DRIF is a SPI like receive only slave device. A general
  15   representation of DRIF interfacing with a master device is shown below.
  16
  17   +---------------------+                +---------------------+
  18   |                     |-----SCK------->|CLK                  |
  19   |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  20   |                     |-----SD0------->|D0                   |
  21   |                     |-----SD1------->|D1                   |
  22   +---------------------+                +---------------------+
  23
  24   As per datasheet, each DRIF channel (drifn) is made up of two internal
  25   channels (drifn0 & drifn1). These two internal channels share the common
  26   CLK & SYNC. Each internal channel has its own dedicated resources like
  27   irq, dma channels, address space & clock. This internal split is not
  28   visible to the external master device.
  29
  30   The device tree model represents each internal channel as a separate node.
  31   The internal channels sharing the CLK & SYNC are tied together by their
  32   phandles using a property called "renesas,bonding". For the rest of
  33   the documentation, unless explicitly stated, the word channel implies an
  34   internal channel.
  35
  36   When both internal channels are enabled they need to be managed together
  37   as one (i.e.) they cannot operate alone as independent devices. Out of the
  38   two, one of them needs to act as a primary device that accepts common
  39   properties of both the internal channels. This channel is identified by a
  40   property called "renesas,primary-bond".
  41
  42   To summarize,
  43      * When both the internal channels that are bonded together are enabled,
  44        the zeroth channel is selected as primary-bond. This channels accepts
  45        properties common to all the members of the bond.
  46      * When only one of the bonded channels need to be enabled, the property
  47        "renesas,bonding" or "renesas,primary-bond" will have no effect. That
  48        enabled channel can act alone as any other independent device.
  49
  50 properties:
  51   compatible:
  52     items:
  53       - enum:
  54           - renesas,r8a7795-drif        # R-Car H3
  55           - renesas,r8a7796-drif        # R-Car M3-W
  56           - renesas,r8a77965-drif       # R-Car M3-N
  57           - renesas,r8a77990-drif       # R-Car E3
  58       - const: renesas,rcar-gen3-drif   # Generic R-Car Gen3 compatible device
  59
  60   reg:
  61     maxItems: 1
  62
  63   interrupts:
  64     maxItems: 1
  65
  66   clocks:
  67     maxItems: 1
  68
  69   clock-names:
  70     items:
  71       - const: fck
  72
  73   resets:
  74     maxItems: 1
  75
  76   dmas:
  77     minItems: 1
  78     maxItems: 2
  79
  80   dma-names:
  81     minItems: 1
  82     items:
  83       - const: rx
  84       - const: rx
  85
  86   renesas,bonding:
  87     $ref: /schemas/types.yaml#/definitions/phandle
  88     description:
  89       The phandle to the other internal channel of DRIF
  90
  91   power-domains:
  92     maxItems: 1
  93
  94   renesas,primary-bond:
  95     type: boolean
  96     description:
  97       Indicates that the channel acts as primary among the bonded channels.
  98
  99   port:
 100     type: object
 101     description:
 102       Child port node corresponding to the data input, in accordance with the
 103       video interface bindings defined in
 104       Documentation/devicetree/bindings/media/video-interfaces.txt.
 105       The port node must contain at least one endpoint.
 106
 107     properties:
 108       endpoint:
 109         type: object
 110
 111         properties:
 112           remote-endpoint:
 113             description:
 114               A phandle to the remote tuner endpoint subnode in remote node
 115               port.
 116
 117           sync-active:
 118             enum: [0, 1]
 119             description:
 120               Indicates sync signal polarity, 0/1 for low/high respectively.
 121               This property maps to SYNCAC bit in the hardware manual. The
 122               default is 1 (active high).
 123
 124         additionalProperties: false
 125
 126 required:
 127   - compatible
 128   - reg
 129   - interrupts
 130   - clocks
 131   - clock-names
 132   - resets
 133   - dmas
 134   - dma-names
 135   - renesas,bonding
 136   - power-domains
 137
 138 allOf:
 139   - if:
 140       required:
 141         - renesas,primary-bond
 142     then:
 143       required:
 144         - pinctrl-0
 145         - pinctrl-names
 146         - port
 147
 148   - if:
 149       required:
 150         - port
 151     then:
 152       required:
 153         - pinctrl-0
 154         - pinctrl-names
 155     else:
 156       properties:
 157         pinctrl-0: false
 158         pinctrl-names: false
 159
 160 additionalProperties: false
 161
 162 examples:
 163   # Example with both internal channels enabled.
 164   #
 165   # When interfacing with a third party tuner device with two data pins as shown
 166   # below.
 167   #
 168   # +---------------------+                +---------------------+
 169   # |                     |-----SCK------->|CLK                  |
 170   # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
 171   # |                     |-----SD0------->|D0                   |
 172   # |                     |-----SD1------->|D1                   |
 173   # +---------------------+                +---------------------+
 174   - |
 175     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
 176     #include <dt-bindings/interrupt-controller/arm-gic.h>
 177     #include <dt-bindings/power/r8a7795-sysc.h>
 178
 179     soc {
 180             #address-cells = <2>;
 181             #size-cells = <2>;
 182
 183             drif00: rif@e6f40000 {
 184                     compatible = "renesas,r8a7795-drif",
 185                                  "renesas,rcar-gen3-drif";
 186                     reg = <0 0xe6f40000 0 0x64>;
 187                     interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 188                     clocks = <&cpg CPG_MOD 515>;
 189                     clock-names = "fck";
 190                     dmas = <&dmac1 0x20>, <&dmac2 0x20>;
 191                     dma-names = "rx", "rx";
 192                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 193                     renesas,bonding = <&drif01>;
 194                     resets = <&cpg 515>;
 195                     renesas,primary-bond;
 196                     pinctrl-0 = <&drif0_pins>;
 197                     pinctrl-names = "default";
 198                     port {
 199                             drif0_ep: endpoint {
 200                                  remote-endpoint = <&tuner_ep>;
 201                             };
 202                     };
 203             };
 204
 205             drif01: rif@e6f50000 {
 206                     compatible = "renesas,r8a7795-drif",
 207                                  "renesas,rcar-gen3-drif";
 208                     reg = <0 0xe6f50000 0 0x64>;
 209                     interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 210                     clocks = <&cpg CPG_MOD 514>;
 211                     clock-names = "fck";
 212                     dmas = <&dmac1 0x22>, <&dmac2 0x22>;
 213                     dma-names = "rx", "rx";
 214                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 215                     renesas,bonding = <&drif00>;
 216                     resets = <&cpg 514>;
 217             };
 218     };
 219
 220   # Example with internal channel 1 alone enabled.
 221   #
 222   # When interfacing with a third party tuner device with one data pin as shown
 223   # below.
 224   #
 225   # +---------------------+                +---------------------+
 226   # |                     |-----SCK------->|CLK                  |
 227   # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
 228   # |                     |                |D0 (unused)          |
 229   # |                     |-----SD-------->|D1                   |
 230   # +---------------------+                +---------------------+
 231   - |
 232     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
 233     #include <dt-bindings/interrupt-controller/arm-gic.h>
 234     #include <dt-bindings/power/r8a7795-sysc.h>
 235
 236     soc {
 237             #address-cells = <2>;
 238             #size-cells = <2>;
 239
 240             drif10: rif@e6f60000 {
 241                     compatible = "renesas,r8a7795-drif",
 242                                  "renesas,rcar-gen3-drif";
 243                     reg = <0 0xe6f60000 0 0x64>;
 244                     interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 245                     clocks = <&cpg CPG_MOD 513>;
 246                     clock-names = "fck";
 247                     dmas = <&dmac1 0x24>, <&dmac2 0x24>;
 248                     dma-names = "rx", "rx";
 249                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 250                     resets = <&cpg 513>;
 251                     renesas,bonding = <&drif11>;
 252                     status = "disabled";
 253             };
 254
 255             drif11: rif@e6f70000 {
 256                     compatible = "renesas,r8a7795-drif",
 257                                  "renesas,rcar-gen3-drif";
 258                     reg = <0 0xe6f70000 0 0x64>;
 259                     interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 260                     clocks = <&cpg CPG_MOD 512>;
 261                     clock-names = "fck";
 262                     dmas = <&dmac1 0x26>, <&dmac2 0x26>;
 263                     dma-names = "rx", "rx";
 264                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 265                     resets = <&cpg 512>;
 266                     renesas,bonding = <&drif10>;
 267                     pinctrl-0 = <&drif1_pins>;
 268                     pinctrl-names = "default";
 269                     port {
 270                             drif1_ep: endpoint {
 271                                  remote-endpoint = <&tuner_ep1>;
 272                                  sync-active = <0>;
 273                             };
 274                     };
 275             };
 276     };
 277 ...