Documentation/devicetree/bindings/media/renesas,drif.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
   8
   9 maintainers:
  10   - Ramesh Shanmugasundaram <rashanmu@gmail.com>
  11   - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
  12
  13 description: |
  14   R-Car Gen3 DRIF is a SPI like receive only slave device. A general
  15   representation of DRIF interfacing with a master device is shown below.
  16
  17   +---------------------+                +---------------------+
  18   |                     |-----SCK------->|CLK                  |
  19   |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
  20   |                     |-----SD0------->|D0                   |
  21   |                     |-----SD1------->|D1                   |
  22   +---------------------+                +---------------------+
  23
  24   As per datasheet, each DRIF channel (drifn) is made up of two internal
  25   channels (drifn0 & drifn1). These two internal channels share the common
  26   CLK & SYNC. Each internal channel has its own dedicated resources like
  27   irq, dma channels, address space & clock. This internal split is not
  28   visible to the external master device.
  29
  30   The device tree model represents each internal channel as a separate node.
  31   The internal channels sharing the CLK & SYNC are tied together by their
  32   phandles using a property called "renesas,bonding". For the rest of
  33   the documentation, unless explicitly stated, the word channel implies an
  34   internal channel.
  35
  36   When both internal channels are enabled they need to be managed together
  37   as one (i.e.) they cannot operate alone as independent devices. Out of the
  38   two, one of them needs to act as a primary device that accepts common
  39   properties of both the internal channels. This channel is identified by a
  40   property called "renesas,primary-bond".
  41
  42   To summarize,
  43      * When both the internal channels that are bonded together are enabled,
  44        the zeroth channel is selected as primary-bond. This channels accepts
  45        properties common to all the members of the bond.
  46      * When only one of the bonded channels need to be enabled, the property
  47        "renesas,bonding" or "renesas,primary-bond" will have no effect. That
  48        enabled channel can act alone as any other independent device.
  49
  50 properties:
  51   compatible:
  52     items:
  53       - enum:
  54           - renesas,r8a7795-drif        # R-Car H3
  55           - renesas,r8a7796-drif        # R-Car M3-W
  56           - renesas,r8a77965-drif       # R-Car M3-N
  57           - renesas,r8a77990-drif       # R-Car E3
  58       - const: renesas,rcar-gen3-drif   # Generic R-Car Gen3 compatible device
  59
  60   reg:
  61     maxItems: 1
  62
  63   interrupts:
  64     maxItems: 1
  65
  66   clocks:
  67     maxItems: 1
  68
  69   clock-names:
  70     maxItems: 1
  71     items:
  72       - const: fck
  73
  74   resets:
  75     maxItems: 1
  76
  77   dmas:
  78     minItems: 1
  79     maxItems: 2
  80
  81   dma-names:
  82     minItems: 1
  83     maxItems: 2
  84     items:
  85       - const: rx
  86       - const: rx
  87
  88   renesas,bonding:
  89     $ref: /schemas/types.yaml#/definitions/phandle
  90     description:
  91       The phandle to the other internal channel of DRIF
  92
  93   power-domains:
  94     maxItems: 1
  95
  96   renesas,primary-bond:
  97     type: boolean
  98     description:
  99       Indicates that the channel acts as primary among the bonded channels.
 100
 101   port:
 102     type: object
 103     description:
 104       Child port node corresponding to the data input, in accordance with the
 105       video interface bindings defined in
 106       Documentation/devicetree/bindings/media/video-interfaces.txt.
 107       The port node must contain at least one endpoint.
 108
 109     properties:
 110       endpoint:
 111         type: object
 112
 113         properties:
 114           remote-endpoint:
 115             description:
 116               A phandle to the remote tuner endpoint subnode in remote node
 117               port.
 118
 119           sync-active:
 120             enum: [0, 1]
 121             description:
 122               Indicates sync signal polarity, 0/1 for low/high respectively.
 123               This property maps to SYNCAC bit in the hardware manual. The
 124               default is 1 (active high).
 125
 126         additionalProperties: false
 127
 128 required:
 129   - compatible
 130   - reg
 131   - interrupts
 132   - clocks
 133   - clock-names
 134   - resets
 135   - dmas
 136   - dma-names
 137   - renesas,bonding
 138   - power-domains
 139
 140 allOf:
 141   - if:
 142       required:
 143         - renesas,primary-bond
 144     then:
 145       required:
 146         - pinctrl-0
 147         - pinctrl-names
 148         - port
 149
 150   - if:
 151       required:
 152         - port
 153     then:
 154       required:
 155         - pinctrl-0
 156         - pinctrl-names
 157     else:
 158       properties:
 159         pinctrl-0: false
 160         pinctrl-names: false
 161
 162 additionalProperties: false
 163
 164 examples:
 165   # Example with both internal channels enabled.
 166   #
 167   # When interfacing with a third party tuner device with two data pins as shown
 168   # below.
 169   #
 170   # +---------------------+                +---------------------+
 171   # |                     |-----SCK------->|CLK                  |
 172   # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
 173   # |                     |-----SD0------->|D0                   |
 174   # |                     |-----SD1------->|D1                   |
 175   # +---------------------+                +---------------------+
 176   - |
 177     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
 178     #include <dt-bindings/interrupt-controller/arm-gic.h>
 179     #include <dt-bindings/power/r8a7795-sysc.h>
 180
 181     soc {
 182             #address-cells = <2>;
 183             #size-cells = <2>;
 184
 185             drif00: rif@e6f40000 {
 186                     compatible = "renesas,r8a7795-drif",
 187                                  "renesas,rcar-gen3-drif";
 188                     reg = <0 0xe6f40000 0 0x64>;
 189                     interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 190                     clocks = <&cpg CPG_MOD 515>;
 191                     clock-names = "fck";
 192                     dmas = <&dmac1 0x20>, <&dmac2 0x20>;
 193                     dma-names = "rx", "rx";
 194                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 195                     renesas,bonding = <&drif01>;
 196                     resets = <&cpg 515>;
 197                     renesas,primary-bond;
 198                     pinctrl-0 = <&drif0_pins>;
 199                     pinctrl-names = "default";
 200                     port {
 201                             drif0_ep: endpoint {
 202                                  remote-endpoint = <&tuner_ep>;
 203                             };
 204                     };
 205             };
 206
 207             drif01: rif@e6f50000 {
 208                     compatible = "renesas,r8a7795-drif",
 209                                  "renesas,rcar-gen3-drif";
 210                     reg = <0 0xe6f50000 0 0x64>;
 211                     interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 212                     clocks = <&cpg CPG_MOD 514>;
 213                     clock-names = "fck";
 214                     dmas = <&dmac1 0x22>, <&dmac2 0x22>;
 215                     dma-names = "rx", "rx";
 216                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 217                     renesas,bonding = <&drif00>;
 218                     resets = <&cpg 514>;
 219             };
 220     };
 221
 222   # Example with internal channel 1 alone enabled.
 223   #
 224   # When interfacing with a third party tuner device with one data pin as shown
 225   # below.
 226   #
 227   # +---------------------+                +---------------------+
 228   # |                     |-----SCK------->|CLK                  |
 229   # |       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
 230   # |                     |                |D0 (unused)          |
 231   # |                     |-----SD-------->|D1                   |
 232   # +---------------------+                +---------------------+
 233   - |
 234     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
 235     #include <dt-bindings/interrupt-controller/arm-gic.h>
 236     #include <dt-bindings/power/r8a7795-sysc.h>
 237
 238     soc {
 239             #address-cells = <2>;
 240             #size-cells = <2>;
 241
 242             drif10: rif@e6f60000 {
 243                     compatible = "renesas,r8a7795-drif",
 244                                  "renesas,rcar-gen3-drif";
 245                     reg = <0 0xe6f60000 0 0x64>;
 246                     interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 247                     clocks = <&cpg CPG_MOD 513>;
 248                     clock-names = "fck";
 249                     dmas = <&dmac1 0x24>, <&dmac2 0x24>;
 250                     dma-names = "rx", "rx";
 251                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 252                     resets = <&cpg 513>;
 253                     renesas,bonding = <&drif11>;
 254                     status = "disabled";
 255             };
 256
 257             drif11: rif@e6f70000 {
 258                     compatible = "renesas,r8a7795-drif",
 259                                  "renesas,rcar-gen3-drif";
 260                     reg = <0 0xe6f70000 0 0x64>;
 261                     interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 262                     clocks = <&cpg CPG_MOD 512>;
 263                     clock-names = "fck";
 264                     dmas = <&dmac1 0x26>, <&dmac2 0x26>;
 265                     dma-names = "rx", "rx";
 266                     power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
 267                     resets = <&cpg 512>;
 268                     renesas,bonding = <&drif10>;
 269                     pinctrl-0 = <&drif1_pins>;
 270                     pinctrl-names = "default";
 271                     port {
 272                             drif1_ep: endpoint {
 273                                  remote-endpoint = <&tuner_ep1>;
 274                                  sync-active = <0>;
 275                             };
 276                     };
 277             };
 278     };
 279 ...