1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/media/renesas,drif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
15 representation of DRIF interfacing with a master device is shown below.
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
20 | |-----SD0------->|D0 |
21 | |-----SD1------->|D1 |
22 +---------------------+ +---------------------+
24 As per datasheet, each DRIF channel (drifn) is made up of two internal
25 channels (drifn0 & drifn1). These two internal channels share the common
26 CLK & SYNC. Each internal channel has its own dedicated resources like
27 irq, dma channels, address space & clock. This internal split is not
28 visible to the external master device.
30 The device tree model represents each internal channel as a separate node.
31 The internal channels sharing the CLK & SYNC are tied together by their
32 phandles using a property called "renesas,bonding". For the rest of
33 the documentation, unless explicitly stated, the word channel implies an
36 When both internal channels are enabled they need to be managed together
37 as one (i.e.) they cannot operate alone as independent devices. Out of the
38 two, one of them needs to act as a primary device that accepts common
39 properties of both the internal channels. This channel is identified by a
40 property called "renesas,primary-bond".
43 * When both the internal channels that are bonded together are enabled,
44 the zeroth channel is selected as primary-bond. This channels accepts
45 properties common to all the members of the bond.
46 * When only one of the bonded channels need to be enabled, the property
47 "renesas,bonding" or "renesas,primary-bond" will have no effect. That
48 enabled channel can act alone as any other independent device.
54 - renesas,r8a7795-drif # R-Car H3
55 - renesas,r8a7796-drif # R-Car M3-W
56 - renesas,r8a77965-drif # R-Car M3-N
57 - renesas,r8a77990-drif # R-Car E3
58 - const: renesas,rcar-gen3-drif # Generic R-Car Gen3 compatible device
87 $ref: /schemas/types.yaml#/definitions/phandle
89 The phandle to the other internal channel of DRIF
97 Indicates that the channel acts as primary among the bonded channels.
102 Child port node corresponding to the data input, in accordance with the
103 video interface bindings defined in
104 Documentation/devicetree/bindings/media/video-interfaces.txt.
105 The port node must contain at least one endpoint.
114 A phandle to the remote tuner endpoint subnode in remote node
120 Indicates sync signal polarity, 0/1 for low/high respectively.
121 This property maps to SYNCAC bit in the hardware manual. The
122 default is 1 (active high).
124 additionalProperties: false
141 - renesas,primary-bond
160 additionalProperties: false
163 # Example with both internal channels enabled.
165 # When interfacing with a third party tuner device with two data pins as shown
168 # +---------------------+ +---------------------+
169 # | |-----SCK------->|CLK |
170 # | Master |-----SS-------->|SYNC DRIFn (slave) |
171 # | |-----SD0------->|D0 |
172 # | |-----SD1------->|D1 |
173 # +---------------------+ +---------------------+
175 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/power/r8a7795-sysc.h>
180 #address-cells = <2>;
183 drif00: rif@e6f40000 {
184 compatible = "renesas,r8a7795-drif",
185 "renesas,rcar-gen3-drif";
186 reg = <0 0xe6f40000 0 0x64>;
187 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&cpg CPG_MOD 515>;
190 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
191 dma-names = "rx", "rx";
192 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
193 renesas,bonding = <&drif01>;
195 renesas,primary-bond;
196 pinctrl-0 = <&drif0_pins>;
197 pinctrl-names = "default";
200 remote-endpoint = <&tuner_ep>;
205 drif01: rif@e6f50000 {
206 compatible = "renesas,r8a7795-drif",
207 "renesas,rcar-gen3-drif";
208 reg = <0 0xe6f50000 0 0x64>;
209 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
210 clocks = <&cpg CPG_MOD 514>;
212 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
213 dma-names = "rx", "rx";
214 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
215 renesas,bonding = <&drif00>;
220 # Example with internal channel 1 alone enabled.
222 # When interfacing with a third party tuner device with one data pin as shown
225 # +---------------------+ +---------------------+
226 # | |-----SCK------->|CLK |
227 # | Master |-----SS-------->|SYNC DRIFn (slave) |
229 # | |-----SD-------->|D1 |
230 # +---------------------+ +---------------------+
232 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
233 #include <dt-bindings/interrupt-controller/arm-gic.h>
234 #include <dt-bindings/power/r8a7795-sysc.h>
237 #address-cells = <2>;
240 drif10: rif@e6f60000 {
241 compatible = "renesas,r8a7795-drif",
242 "renesas,rcar-gen3-drif";
243 reg = <0 0xe6f60000 0 0x64>;
244 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cpg CPG_MOD 513>;
247 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
248 dma-names = "rx", "rx";
249 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
251 renesas,bonding = <&drif11>;
255 drif11: rif@e6f70000 {
256 compatible = "renesas,r8a7795-drif",
257 "renesas,rcar-gen3-drif";
258 reg = <0 0xe6f70000 0 0x64>;
259 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&cpg CPG_MOD 512>;
262 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
263 dma-names = "rx", "rx";
264 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
266 renesas,bonding = <&drif10>;
267 pinctrl-0 = <&drif1_pins>;
268 pinctrl-names = "default";
271 remote-endpoint = <&tuner_ep1>;