1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm CAMSS ISP
11 - Robert Foss <robert.foss@linaro.org>
12 - Todor Tomov <todor.too@gmail.com>
15 The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
19 const: qcom,msm8916-camss
29 - const: csiphy0_timer
30 - const: csiphy1_timer
65 - description: VFE GDSC - Video Front End, Global Distributed Switch Controller.
68 $ref: /schemas/graph.yaml#/properties/ports
75 $ref: /schemas/graph.yaml#/$defs/port-base
76 unevaluatedProperties: false
78 Input port for receiving CSI data.
82 $ref: video-interfaces.yaml#
83 unevaluatedProperties: false
92 An array of physical data lanes indexes.
93 Position of an entry determines the logical
94 lane number, while the value of an entry
95 indicates physical lane index. Lane swapping
96 is supported. Physical lane indexes;
106 $ref: /schemas/graph.yaml#/$defs/port-base
107 unevaluatedProperties: false
109 Input port for receiving CSI data.
113 $ref: video-interfaces.yaml#
114 unevaluatedProperties: false
136 - const: csiphy0_clk_mux
138 - const: csiphy1_clk_mux
147 Definition of the regulator used as analog power supply.
161 additionalProperties: false
165 #include <dt-bindings/interrupt-controller/arm-gic.h>
166 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
168 camss: camss@1b00000 {
169 compatible = "qcom,msm8916-camss";
171 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
172 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
173 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
174 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
175 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
176 <&gcc GCC_CAMSS_CSI0_CLK>,
177 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
178 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
179 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
180 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
181 <&gcc GCC_CAMSS_CSI1_CLK>,
182 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
183 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
184 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
185 <&gcc GCC_CAMSS_AHB_CLK>,
186 <&gcc GCC_CAMSS_VFE0_CLK>,
187 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
188 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
189 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
191 clock-names = "top_ahb",
211 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
212 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
213 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
214 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
215 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
216 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
218 interrupt-names = "csiphy0",
225 iommus = <&apps_iommu 3>;
227 power-domains = <&gcc VFE_GDSC>;
229 reg = <0x01b0ac00 0x200>,
239 reg-names = "csiphy0",
249 vdda-supply = <®_2v8>;
252 #address-cells = <1>;