1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
15 receiver IP core named CSIS. The IP core originates from Samsung, and may be
16 compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
17 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
20 completely wrapped by the CSIS and doesn't expose a control interface of its
21 own. This binding thus covers both IP cores.
27 - fsl,imx8mm-mipi-csi2
38 - description: The peripheral clock (a.k.a. APB clock)
39 - description: The external clock (optionally used as the pixel clock)
40 - description: The MIPI D-PHY clock
41 - description: The AXI clock
55 description: The MIPI D-PHY digital power supply
59 - description: MIPI D-PHY slave reset
62 description: The desired external clock ("wrap") frequency, in Hz
66 $ref: /schemas/graph.yaml#/properties/ports
70 $ref: /schemas/graph.yaml#/$defs/port-base
71 unevaluatedProperties: false
73 Input port node, single endpoint describing the CSI-2 transmitter.
77 $ref: video-interfaces.yaml#
78 unevaluatedProperties: false
99 const: fsl,imx7-mipi-csi2
107 $ref: /schemas/graph.yaml#/properties/port
120 additionalProperties: false
127 const: fsl,imx7-mipi-csi2
143 #include <dt-bindings/clock/imx7d-clock.h>
144 #include <dt-bindings/interrupt-controller/arm-gic.h>
145 #include <dt-bindings/interrupt-controller/irq.h>
146 #include <dt-bindings/reset/imx7-reset.h>
149 compatible = "fsl,imx7-mipi-csi2";
150 reg = <0x30750000 0x10000>;
151 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
154 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
155 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
156 clock-names = "pclk", "wrap", "phy";
157 clock-frequency = <166000000>;
159 power-domains = <&pgc_mipi_phy>;
160 phy-supply = <®_1p0d>;
161 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
164 #address-cells = <1>;
170 mipi_from_sensor: endpoint {
171 remote-endpoint = <&ov2680_to_mipi>;
179 mipi_vc0_to_csi_mux: endpoint {
180 remote-endpoint = <&csi_mux_from_mipi_vc0>;
187 #include <dt-bindings/clock/imx8mm-clock.h>
188 #include <dt-bindings/interrupt-controller/arm-gic.h>
189 #include <dt-bindings/interrupt-controller/irq.h>
192 compatible = "fsl,imx8mm-mipi-csi2";
193 reg = <0x32e30000 0x1000>;
194 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
195 clock-frequency = <333000000>;
196 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
197 <&clk IMX8MM_CLK_CSI1_ROOT>,
198 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
199 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
200 clock-names = "pclk", "wrap", "phy", "axi";
201 power-domains = <&mipi_pd>;
206 #address-cells = <1>;
212 imx8mm_mipi_csi_in: endpoint {
213 remote-endpoint = <&imx477_out>;
214 data-lanes = <1 2 3 4>;
221 imx8mm_mipi_csi_out: endpoint {
222 remote-endpoint = <&csi_in>;