1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 $id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Mediatek Video Decode Accelerator With Multi Hardware
11 - Yunfei Dong <yunfei.dong@mediatek.com>
14 Mediatek Video Decode is the video decode hardware present in Mediatek
15 SoCs which supports high resolution decoding functionalities. Required
16 parent and child device node.
18 About the Decoder Hardware Block Diagram, please check below:
20 +---------------------------------+------------------------------------+
22 | input -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------------+---------------------||-------------+
25 lat workqueue | core workqueue <parent>
26 -------------||-----------------------------------------||------------------
28 \/ <----------------HW index-------------->\/
29 +------------------------------------------------------+
31 | clk power irq iommu |
32 | (lat/lat soc/core0/core1) |
33 +------------------------------------------------------+
35 As above, there are parent and child devices, child mean each hardware. The child device
36 controls the information of each hardware independent which include clk/power/irq.
38 There are two workqueues in parent device: lat workqueue and core workqueue. They are used
39 to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
40 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
42 writing the result to output buffer, disable hardware when core decode done. These two
43 hardwares will decode each frame cyclically.
45 For the smi common may not the same for each hardware, can't combine all hardware in one node,
46 or leading to iommu fault when access dram data.
50 const: mediatek,mt8192-vcodec-dec
59 List of the hardware port in respective IOMMU block for current Socs.
60 Refer to bindings/iommu/mediatek,iommu.yaml.
63 $ref: /schemas/types.yaml#/definitions/phandle
66 The node of system control processor (SCP), using
67 the remoteproc & rpmsg framework.
72 Describes the physical address space of IOMMU maps to memory.
82 # Required child node:
84 '^vcodec-lat@[0-9a-f]+$':
89 const: mediatek,mtk-vcodec-lat
101 List of the hardware port in respective IOMMU block for current Socs.
102 Refer to bindings/iommu/mediatek,iommu.yaml.
118 assigned-clock-parents:
132 - assigned-clock-parents
135 additionalProperties: false
137 '^vcodec-core@[0-9a-f]+$':
142 const: mediatek,mtk-vcodec-core
154 List of the hardware port in respective IOMMU block for current Socs.
155 Refer to bindings/iommu/mediatek,iommu.yaml.
171 assigned-clock-parents:
185 - assigned-clock-parents
188 additionalProperties: false
198 additionalProperties: false
202 #include <dt-bindings/interrupt-controller/arm-gic.h>
203 #include <dt-bindings/memory/mt8192-larb-port.h>
204 #include <dt-bindings/interrupt-controller/irq.h>
205 #include <dt-bindings/clock/mt8192-clk.h>
206 #include <dt-bindings/power/mt8192-power.h>
209 #address-cells = <2>;
211 ranges = <0 0x16000000 0x16000000 0 0x40000>;
213 video-codec@16000000 {
214 compatible = "mediatek,mt8192-vcodec-dec";
215 mediatek,scp = <&scp>;
216 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
217 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
218 #address-cells = <2>;
220 ranges = <0 0 0 0x16000000 0 0x40000>;
221 reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
223 compatible = "mediatek,mtk-vcodec-lat";
224 reg = <0 0x10000 0 0x800>;
225 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
226 iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
227 <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
228 <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
229 <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
230 <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
231 <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
232 <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
233 <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
234 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
235 <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
236 <&vdecsys_soc CLK_VDEC_SOC_LAT>,
237 <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
238 <&topckgen CLK_TOP_MAINPLL_D4>;
239 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
240 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
241 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
242 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
246 compatible = "mediatek,mtk-vcodec-core";
247 reg = <0 0x25000 0 0x1000>;
248 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
249 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
250 <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
251 <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
252 <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
253 <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
254 <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
255 <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
256 <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
257 <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
258 <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
259 <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
260 clocks = <&topckgen CLK_TOP_VDEC_SEL>,
261 <&vdecsys CLK_VDEC_VDEC>,
262 <&vdecsys CLK_VDEC_LAT>,
263 <&vdecsys CLK_VDEC_LARB1>,
264 <&topckgen CLK_TOP_MAINPLL_D4>;
265 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
266 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
267 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
268 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;