Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Allwinner A31 CMOS Sensor Interface (CSI) Device Tree Bindings
   8
   9 maintainers:
  10   - Chen-Yu Tsai <wens@csie.org>
  11   - Maxime Ripard <mripard@kernel.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - allwinner,sun6i-a31-csi
  17       - allwinner,sun8i-a83t-csi
  18       - allwinner,sun8i-h3-csi
  19       - allwinner,sun8i-v3s-csi
  20       - allwinner,sun50i-a64-csi
  21
  22   reg:
  23     maxItems: 1
  24
  25   interrupts:
  26     maxItems: 1
  27
  28   clocks:
  29     items:
  30       - description: Bus Clock
  31       - description: Module Clock
  32       - description: DRAM Clock
  33
  34   clock-names:
  35     items:
  36       - const: bus
  37       - const: mod
  38       - const: ram
  39
  40   resets:
  41     maxItems: 1
  42
  43   port:
  44     $ref: /schemas/graph.yaml#/$defs/port-base
  45
  46     properties:
  47       endpoint:
  48         $ref: video-interfaces.yaml#
  49         unevaluatedProperties: false
  50
  51         properties:
  52           bus-width:
  53             enum: [ 8, 10, 12, 16 ]
  54
  55           pclk-sample: true
  56           hsync-active: true
  57           vsync-active: true
  58
  59         required:
  60           - bus-width
  61
  62     additionalProperties: false
  63
  64 required:
  65   - compatible
  66   - reg
  67   - interrupts
  68   - clocks
  69   - clock-names
  70   - resets
  71
  72 additionalProperties: false
  73
  74 examples:
  75   - |
  76     #include <dt-bindings/interrupt-controller/arm-gic.h>
  77     #include <dt-bindings/clock/sun8i-v3s-ccu.h>
  78     #include <dt-bindings/reset/sun8i-v3s-ccu.h>
  79
  80     csi1: csi@1cb4000 {
  81         compatible = "allwinner,sun8i-v3s-csi";
  82         reg = <0x01cb4000 0x1000>;
  83         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
  84         clocks = <&ccu CLK_BUS_CSI>,
  85                  <&ccu CLK_CSI1_SCLK>,
  86                  <&ccu CLK_DRAM_CSI>;
  87         clock-names = "bus",
  88                       "mod",
  89                       "ram";
  90         resets = <&ccu RST_BUS_CSI>;
  91
  92         port {
  93             /* Parallel bus endpoint */
  94             csi1_ep: endpoint {
  95                 remote-endpoint = <&adv7611_ep>;
  96                 bus-width = <16>;
  97
  98                 /*
  99                  * If hsync-active/vsync-active are missing,
 100                  * embedded BT.656 sync is used.
 101                  */
 102                  hsync-active = <0>; /* Active low */
 103                  vsync-active = <0>; /* Active low */
 104                  pclk-sample = <1>;  /* Rising */
 105             };
 106         };
 107     };
 108
 109 ...