Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml

   1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
   8
   9 maintainers:
  10   - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  11
  12 description:
  13   The Inter-Processor Communication Controller (IPCC) is a centralized hardware
  14   to route interrupts across various subsystems. It involves a three-level
  15   addressing scheme called protocol, client and signal. For example, consider an
  16   entity on the Application Processor Subsystem (APSS) that wants to listen to
  17   Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
  18   a case, the client would be Modem (client-id is 2) and the signal would be
  19   SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
  20   protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
  21   for the list of such IDs.
  22
  23 properties:
  24   compatible:
  25     items:
  26       - enum:
  27           - qcom,sm8250-ipcc
  28       - const: qcom,ipcc
  29
  30   reg:
  31     maxItems: 1
  32
  33   interrupts:
  34     maxItems: 1
  35
  36   interrupt-controller: true
  37
  38   "#interrupt-cells":
  39     const: 3
  40     description:
  41       The first cell is the client-id, the second cell is the signal-id and the
  42       third cell is the interrupt type.
  43
  44   "#mbox-cells":
  45     const: 2
  46     description:
  47       The first cell is the client-id, and the second cell is the signal-id.
  48
  49 required:
  50   - compatible
  51   - reg
  52   - interrupts
  53   - interrupt-controller
  54   - "#interrupt-cells"
  55   - "#mbox-cells"
  56
  57 additionalProperties: false
  58
  59 examples:
  60   - |
  61         #include <dt-bindings/interrupt-controller/arm-gic.h>
  62         #include <dt-bindings/mailbox/qcom-ipcc.h>
  63
  64         mailbox@408000 {
  65                 compatible = "qcom,sm8250-ipcc", "qcom,ipcc";
  66                 reg = <0x408000 0x1000>;
  67                 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
  68                 interrupt-controller;
  69                 #interrupt-cells = <3>;
  70                 #mbox-cells = <2>;
  71         };
  72
  73         smp2p-modem {
  74                 compatible = "qcom,smp2p";
  75                 interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS
  76                                 IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>;
  77                 mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
  78
  79                 /* Other SMP2P fields */
  80         };