1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Messaging Unit (MU)
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The Messaging Unit module enables two processors within the SoC to
14 communicate and coordinate by passing messages (e.g. data, status
15 and control) through the MU interface. The MU also provides the ability
16 for one processor to signal the other processor using interrupts.
18 Because the MU manages the messaging between processors, the MU uses
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
21 other. The MU accomplishes synchronization using two sets of matching
22 registers (Processor A-facing, Processor B-facing).
27 - const: fsl,imx6sx-mu
28 - const: fsl,imx7ulp-mu
29 - const: fsl,imx8-mu-scu
38 - const: fsl,imx6sx-mu
39 - description: To communicate with i.MX8 SCU with fast IPC
41 - const: fsl,imx8qxp-mu
42 - const: fsl,imx8-mu-scu
52 <&phandle type channel>
53 phandle : Label name of controller
55 channel : Channel number
57 This MU support 4 type of unidirectional channels, each type
58 has 4 channels. A total of 16 channels. Following types are
60 0 - TX channel with 32bit transmit register and IRQ transmit
61 acknowledgment support.
62 1 - RX channel with 32bit receive register and IRQ support
63 2 - TX doorbell channel. Without own register and no ACK support.
64 3 - RX doorbell channel.
71 description: boolean, if present, means it is for side B MU.
80 additionalProperties: false
84 #include <dt-bindings/interrupt-controller/arm-gic.h>
87 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
88 reg = <0x5d1b0000 0x10000>;
89 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;