Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Texas Instruments K3 Interrupt Aggregator
   8
   9 maintainers:
  10   - Lokesh Vutla <lokeshvutla@ti.com>
  11
  12 allOf:
  13   - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
  14
  15 description: |
  16   The Interrupt Aggregator (INTA) provides a centralized machine
  17   which handles the termination of system events to that they can
  18   be coherently processed by the host(s) in the system. A maximum
  19   of 64 events can be mapped to a single interrupt.
  20
  21                                 Interrupt Aggregator
  22                        +-----------------------------------------+
  23                        |      Intmap            VINT             |
  24                        | +--------------+  +------------+        |
  25               m ------>| | vint  | bit  |  | 0 |.....|63| vint0  |
  26                  .     | +--------------+  +------------+        |      +------+
  27                  .     |         .               .               |      | HOST |
  28   Globalevents  ------>|         .               .               |----->| IRQ  |
  29                  .     |         .               .               |      | CTRL |
  30                  .     |         .               .               |      +------+
  31               n ------>| +--------------+  +------------+        |
  32                        | | vint  | bit  |  | 0 |.....|63| vintx  |
  33                        | +--------------+  +------------+        |
  34                        |                                         |
  35                        +-----------------------------------------+
  36
  37   Configuration of these Intmap registers that maps global events to vint is
  38   done by a system controller (like the Device Memory and Security Controller
  39   on AM654 SoC). Driver should request the system controller to get the range
  40   of global events and vints assigned to the requesting host. Management
  41   of these requested resources should be handled by driver and requests
  42   system controller to map specific global event to vint, bit pair.
  43
  44   Communication between the host processor running an OS and the system
  45   controller happens through a protocol called TI System Control Interface
  46   (TISCI protocol).
  47
  48 properties:
  49   compatible:
  50     const: ti,sci-inta
  51
  52   reg:
  53     maxItems: 1
  54
  55   interrupt-controller: true
  56
  57   msi-controller: true
  58
  59   ti,interrupt-ranges:
  60     $ref: /schemas/types.yaml#/definitions/uint32-matrix
  61     description: |
  62       Interrupt ranges that converts the INTA output hw irq numbers
  63       to parents's input interrupt numbers.
  64     items:
  65       items:
  66         - description: |
  67             "output_irq" specifies the base for inta output irq
  68         - description: |
  69             "parent's input irq" specifies the base for parent irq
  70         - description: |
  71             "limit" specifies the limit for translation
  72
  73 required:
  74   - compatible
  75   - reg
  76   - interrupt-controller
  77   - msi-controller
  78   - ti,sci
  79   - ti,sci-dev-id
  80   - ti,interrupt-ranges
  81
  82 examples:
  83   - |
  84     bus {
  85         #address-cells = <2>;
  86         #size-cells = <2>;
  87
  88         main_udmass_inta: msi-controller@33d00000 {
  89             compatible = "ti,sci-inta";
  90             reg = <0x0 0x33d00000 0x0 0x100000>;
  91             interrupt-controller;
  92             msi-controller;
  93             interrupt-parent = <&main_navss_intr>;
  94             ti,sci = <&dmsc>;
  95             ti,sci-dev-id = <179>;
  96             ti,interrupt-ranges = <0 0 256>;
  97         };
  98     };