1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 Interrupt Aggregator
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Aggregator (INTA) provides a centralized machine
17 which handles the termination of system events to that they can
18 be coherently processed by the host(s) in the system. A maximum
19 of 64 events can be mapped to a single interrupt.
22 +-----------------------------------------+
24 | +--------------+ +------------+ |
25 m ------>| | vint | bit | | 0 |.....|63| vint0 |
26 . | +--------------+ +------------+ | +------+
28 Globalevents ------>| . . |----->| IRQ |
31 n ------>| +--------------+ +------------+ |
32 | | vint | bit | | 0 |.....|63| vintx |
33 | +--------------+ +------------+ |
37 Unmapped events ---->| | umapidx |-------------------------> Globalevents
40 +-----------------------------------------+
42 Configuration of these Intmap registers that maps global events to vint is
43 done by a system controller (like the Device Memory and Security Controller
44 on AM654 SoC). Driver should request the system controller to get the range
45 of global events and vints assigned to the requesting host. Management
46 of these requested resources should be handled by driver and requests
47 system controller to map specific global event to vint, bit pair.
49 Communication between the host processor running an OS and the system
50 controller happens through a protocol called TI System Control Interface
60 interrupt-controller: true
65 $ref: /schemas/types.yaml#/definitions/uint32-matrix
67 Interrupt ranges that converts the INTA output hw irq numbers
68 to parents's input interrupt numbers.
72 "output_irq" specifies the base for inta output irq
74 "parent's input irq" specifies the base for parent irq
76 "limit" specifies the limit for translation
78 ti,unmapped-event-sources:
79 $ref: /schemas/types.yaml#/definitions/phandle-array
81 Array of phandles to DMA controllers where the unmapped events originate.
86 - interrupt-controller
92 unevaluatedProperties: false
100 main_udmass_inta: msi-controller@33d00000 {
101 compatible = "ti,sci-inta";
102 reg = <0x0 0x33d00000 0x0 0x100000>;
103 interrupt-controller;
105 interrupt-parent = <&main_navss_intr>;
107 ti,sci-dev-id = <179>;
108 ti,interrupt-ranges = <0 0 256>;