1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19 privilege modes per hart; machine mode and supervisor mode.
21 Each interrupt can be enabled on per-context basis. Any context can claim
22 a pending enabled interrupt and then release it once it has been handled.
24 Each interrupt has a configurable priority. Higher priority interrupts are
25 serviced first. Each context can specify a priority threshold. Interrupts
26 with priority below this threshold will not cause the PLIC to raise its
27 interrupt line leading to the context.
29 While the PLIC supports both edge-triggered and level-triggered interrupts,
30 interrupt handlers are oblivious to this distinction and therefore it is not
31 specified in the PLIC device-tree binding.
33 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
34 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
35 contains a specific memory layout, which is documented in chapter 8 of the
36 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
39 - Sagar Kadam <sagar.kadam@sifive.com>
40 - Paul Walmsley <paul.walmsley@sifive.com>
41 - Palmer Dabbelt <palmer@dabbelt.com>
47 - sifive,fu540-c000-plic
49 - const: sifive,plic-1.0.0
60 interrupt-controller: true
65 Specifies which contexts are connected to the PLIC, with "-1" specifying
66 that a context is not present. Each node pointed to should be a
67 riscv,cpu-intc node, which has a riscv node as parent.
70 $ref: "/schemas/types.yaml#/definitions/uint32"
72 Specifies how many external interrupts are supported by this controller.
78 - interrupt-controller
83 additionalProperties: false
87 plic: interrupt-controller@c000000 {
89 #interrupt-cells = <1>;
90 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
92 interrupts-extended = <
94 &cpu1_intc 11 &cpu1_intc 9
95 &cpu2_intc 11 &cpu2_intc 9
96 &cpu3_intc 11 &cpu3_intc 9
97 &cpu4_intc 11 &cpu4_intc 9>;
98 reg = <0xc000000 0x4000000>;