1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A1 Interrupt Controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and
16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts,
20 - $ref: /schemas/interrupt-controller.yaml#
26 - renesas,r7s72100-irqc # RZ/A1H
27 - renesas,r7s9210-irqc # RZ/A2M
28 - const: renesas,rza1-irqc
36 interrupt-controller: true
43 description: Specifies the mapping from external interrupts to GIC interrupts.
54 - interrupt-controller
59 additionalProperties: false
63 #include <dt-bindings/interrupt-controller/arm-gic.h>
64 irqc: interrupt-controller@fcfef800 {
65 compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
66 #interrupt-cells = <2>;
69 reg = <0xfcfef800 0x6>;
71 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
72 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
73 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
74 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
75 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
76 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
77 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
78 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
79 interrupt-map-mask = <7 0>;